Laleh Behjat

According to our database1, Laleh Behjat authored at least 56 papers between 1999 and 2022.

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Bibliography

2022
Algorithm Selection Framework for Legalization Using Deep Convolutional Neural Networks and Transfer Learning.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

2021
ILP-Based Global Routing Optimization with Cell Movements.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2021

2020
Eh?Predictor: A Deep Learning Framework to Identify Detailed Routing Short Violations From a Placed Netlist.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

2019
An Optimized Cost Flow Algorithm to Spread Cells in Detailed Placement.
ACM Trans. Design Autom. Electr. Syst., 2019

2018
Eh?Legalizer: A High Performance Standard-Cell Legalizer Observing Technology Constraints.
ACM Trans. Design Autom. Electr. Syst., 2018

A machine learning framework to identify detailed routing short violations from a placed netlist.
Proceedings of the 55th Annual Design Automation Conference, 2018

2017
A Multiobjective Cooptimization of Buffer and Wire Sizes in High-Performance Clock Trees.
IEEE Trans. Circuits Syst. II Express Briefs, 2017

Detailed routing violation prediction during placement using machine learning.
Proceedings of the 2017 International Symposium on VLSI Design, Automation and Test, 2017

A Fast, Robust Network Flow-based Standard-Cell Legalization Method for Minimizing Maximum Movement.
Proceedings of the 2017 ACM on International Symposium on Physical Design, 2017

DATC RDF: Robust design flow database: Invited paper.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

An efficient optimal clock network buffer sizing with slew consideration.
Proceedings of the 30th IEEE Canadian Conference on Electrical and Computer Engineering, 2017

2016
Eh?Placer: A High-Performance Modern Technology-Driven Placer.
ACM Trans. Design Autom. Electr. Syst., 2016

A High-Performance Complexity Reduced Behavioral Model and Digital Predistorter for MIMO Systems With Crosstalk.
IEEE Trans. Commun., 2016

A fast force-directed simulated annealing for 3D IC partitioning.
Integr., 2016

Routing-Aware Incremental Timing-Driven Placement.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

OpenDesign flow database: the infrastructure for VLSI design and design automation research.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

Exploring Electrical Engineering through movement: Going with the Flow and Programming Puzzles.
Proceedings of the 2016 IEEE Frontiers in Education Conference, 2016

Using gamification for engagement and learning in electrical and computer engineering classrooms.
Proceedings of the 2016 IEEE Frontiers in Education Conference, 2016

2015
Enhancing EDA education through gamification.
Proceedings of the 2015 IEEE International Conference on Microelectronics Systems Education, 2015

The impact of industry-organized contests on EDA education.
Proceedings of the 2015 IEEE International Conference on Microelectronics Systems Education, 2015

A Detailed Routing-Aware Detailed Placement Technique.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

High Performance Global Placement and Legalization Accounting for Fence Regions.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

2014
Variation-Aware Geometric Programming Models for the Clock Network Buffer Sizing Problem.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Optimal gate sizing using a self-tuning multi-objective framework.
Integr., 2014

Detailed placement accounting for technology constraints.
Proceedings of the 22nd International Conference on Very Large Scale Integration, 2014

2013
A new a priori net length estimation technique for integrated circuits using radial basis functions.
Comput. Electr. Eng., 2013

An analog-design assistant tool and an example of its application.
Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013

Integrating creativity into elementary electrical engineering education using CDIO and project-based learning.
Proceedings of the 2013 IEEE International Conference on Microelectronic Systems Education, 2013

ISPD 2013 expert designer/user session (eds).
Proceedings of the International Symposium on Physical Design, 2013

Buffer sizing for clock networks using robust geometric programming considering variations in buffer sizes.
Proceedings of the International Symposium on Physical Design, 2013

A self-tuning multi-objective optimization framework for geometric programming with gate sizing applications.
Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013

2012
A New Length-Based Algebraic Multigrid Clustering Algorithm.
VLSI Design, 2012

An algebraic multigrid-based algorithm for circuit clustering.
Appl. Math. Comput., 2012

Analysis of post-placement length estimation.
Proceedings of the International Workshop on System Level Interconnect Prediction, 2012

Parallel clock tree synthesis.
Proceedings of the 25th IEEE Canadian Conference on Electrical and Computer Engineering, 2012

2011
A pre-placement individual net length estimation model and an application for modern circuits.
Integr., 2011

Wirelength and congestion estimation for routability-driven placement.
Proceedings of the 2011 International Workshop on System Level Interconnect Prediction, 2011

2009
A Multilevel Congestion-Based Global Router.
VLSI Design, 2009

A pre-placement net length estimation technique for mixed-size circuits.
Proceedings of the 11th International Workshop on System-Level Interconnect Prediction (SLIP 2009), 2009

2007
Net Cluster: A Net-Reduction-Based Clustering Preprocessing Algorithm for Partitioning and Placement.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

An effective clustering algorithm for mixed-size placement.
Proceedings of the 2007 International Symposium on Physical Design, 2007

Two Clustering Preprocessing Techniques for Large-Scale Circuits.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Floorplan repair using dynamic whitespace management.
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

Clustering algorithms for circuit partitioning and placement problems.
Proceedings of the 18th European Conference on Circuit Theory and Design, 2007

2006
A connectivity based clustering algorithm with application to VLSI circuit partitioning.
IEEE Trans. Circuits Syst. II Express Briefs, 2006

Integer Linear Programming Models for Global Routing.
INFORMS J. Comput., 2006

Interior point models for power system stability problems.
Eur. J. Oper. Res., 2006

A Structural Study and Hyperedge Clustering Technique for Large Scale Circuits.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2006

Net cluster: a net-reduction based clustering preprocessing algorithm.
Proceedings of the 2006 International Symposium on Physical Design, 2006

2005
A Multivalue Eigenvalue Based Circuit Partitioning Technique.
Proceedings of the 5th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC 2005), 2005

A Structure Based Clustering Algorithm with Applications to VLSI Physical Design.
Proceedings of the 5th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC 2005), 2005

Coordinated static stability margin management of inter-regional electricity systems.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Fast integer linear programming based models for VLSI global routing.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2003
Steiner Tree Construction Based on Congestion for the Global Routing Problem.
Proceedings of the 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC'03), 30 June, 2003

2002
A Novel Eigenvector Technique for Large Scale Combinatorial Problems in VLSI Layout.
J. Comb. Optim., 2002

1999
VLSI concentric partitioning using interior point quadratic programming.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999


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