Renu Rangnekar

According to our database1, Renu Rangnekar authored at least 2 papers between 2007 and 2009.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of five.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2009
A 2.4Gbps-4.8Gbps XDR-DRAM I/O (XIO) Link.
Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009

2007
A 2.5Gbps Quad CMOS Transceiver Cell Using Regulated Supply Low Jitter PLL.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007


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