Leneesh Raghavan

According to our database1, Leneesh Raghavan authored at least 7 papers between 2009 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2019
A Fast T&H Overcurrent Detector for a Spinning Hall Current Sensor With Ping-Pong and Chopping Techniques.
IEEE J. Solid State Circuits, 2019

2018
A Signal and Offset T&H Frontend for Spinning Hall Sensors with Ping-Pong and Chopping Techniques.
Proceedings of the 44th IEEE European Solid State Circuits Conference, 2018

2012
A Tri-Modal 20-Gbps/Link Differential/DDR3/GDDR5 Memory Interface.
IEEE J. Solid State Circuits, 2012

A 12.8-Gb/s/link Tri-Modal Single-Ended Memory Interface.
IEEE J. Solid State Circuits, 2012

2010
Architectural Comparison of Analog and Digital Duty Cycle Corrector for High Speed I/O Link.
Proceedings of the VLSI Design 2010: 23rd International Conference on VLSI Design, 2010

2009
A 2.4Gbps-4.8Gbps XDR-DRAM I/O (XIO) Link.
Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009

Reduction of Current Mismatch in PLL Charge Pump.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2009


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