Mahabaleshwara

According to our database1, Mahabaleshwara authored at least 3 papers between 2007 and 2012.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2012
A Tri-Modal 20-Gbps/Link Differential/DDR3/GDDR5 Memory Interface.
IEEE J. Solid State Circuits, 2012

A 12.8-Gb/s/link Tri-Modal Single-Ended Memory Interface.
IEEE J. Solid State Circuits, 2012

2007
A 2.5Gbps Quad CMOS Transceiver Cell Using Regulated Supply Low Jitter PLL.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007


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