Reza Lotfi
Orcid: 0000-0001-5868-8467
According to our database1,
Reza Lotfi
authored at least 79 papers
between 2003 and 2025.
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Bibliography
2025
A viable and bi-level supply chain network design by applying risk, robustness and considering environmental requirements.
Central Eur. J. Oper. Res., December, 2025
A viable relief supply chain network design by considering risk and robustness for disaster and crisis management.
Central Eur. J. Oper. Res., December, 2025
Antifragile, sustainable and agile healthcare waste chain network design by considering blockchain, resiliency, robustness and risk.
Central Eur. J. Oper. Res., September, 2025
A robust, resilience machine learning with risk approach: a case study of gas consumption.
Ann. Oper. Res., August, 2025
Viable supply chain with vendor-managed inventory approach by considering blockchain, risk and robustness.
Ann. Oper. Res., January, 2025
2024
An extended robust mathematical model to project the course of COVID-19 epidemic in Iran.
Ann. Oper. Res., August, 2024
An Improved Readout Circuit for Enhanced Accuracy and Frame Rate in Large Resistive Sensor Arrays Using Adaptive Techniques.
IEEE Trans. Instrum. Meas., 2024
A Robust, resilience and risk-aware solar energy farm location by Bi-Level programming approach.
RAIRO Oper. Res., 2024
A Robust and Risk-Averse Medical Waste Chain Network Design by considering Viability requirements.
RAIRO Oper. Res., 2024
A viable supplier selection with order allocation by considering robustness, risk-averse and blockchain technology.
Comput. Ind. Eng., 2024
2023
Robust optimization for energy-aware cryptocurrency farm location with renewable energy.
Comput. Ind. Eng., March, 2023
Robust and resilience budget allocation for projects with a risk-averse approach: A case study in healthcare projects.
Comput. Ind. Eng., February, 2023
2022
IEEE Trans. Circuits Syst. II Express Briefs, 2022
Sustainable Earthquake Resilience with the Versatile Shape Memory Alloy (SMA)-Based Superelasticity-Assisted Slider.
Sensors, 2022
Versatile DAC-less successive approximation ADC architecture for medium speed data acquisition.
Microelectron. J., 2022
Hybrid Fuzzy and Data-Driven Robust Optimization for Resilience and Sustainable Health Care Supply Chain with Vendor-Managed Inventory Approach.
Int. J. Fuzzy Syst., 2022
A 10-b 330nW Third-Order Predictive SAR ADC Dedicated to Neural Recording Brain Implants.
Proceedings of the 20th IEEE Interregional NEWCAS Conference, 2022
2020
IEEE Trans. Circuits Syst. II Express Briefs, 2020
Revisiting element removal for density-based structural topology optimization with reintroduction by Heaviside projection.
CoRR, 2020
2017
IEEE Trans. Very Large Scale Integr. Syst., 2017
A Charge-Redistribution Phase-Domain ADC Using an IQ-Assisted Binary-Search Algorithm.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017
IEEE Trans. Circuits Syst. II Express Briefs, 2017
A low-power capacitor switching scheme with low common-mode voltage variation for successive approximation ADC.
Microelectron. J., 2017
A Multi-Objective and Multi-Product Advertising Billboard Location Model with Attraction Factor Mathematical Modeling and Solutions.
Int. J. Appl. Logist., 2017
2016
Proceedings of the IEEE 59th International Midwest Symposium on Circuits and Systems, 2016
2015
IEEE Trans. Circuits Syst. I Regul. Pap., 2015
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
2014
IEEE Trans. Very Large Scale Integr. Syst., 2014
IEEE Trans. Very Large Scale Integr. Syst., 2014
IEEE J. Biomed. Health Informatics, 2014
A 10-bit 110 kS/s 1.16 µW SA-ADC With a Hybrid Differential/Single-Ended DAC in 180-nm CMOS for Multichannel Biomedical Applications.
IEEE Trans. Circuits Syst. II Express Briefs, 2014
IEEE Trans. Circuits Syst. II Express Briefs, 2014
Nonlinear Signal-Specific ADC for Efficient Neural Recording in Brain-Machine Interfaces.
IEEE Trans. Biomed. Circuits Syst., 2014
2012
Impacts of NBTI/PBTI on performance of domino logic circuits with high-k metal-gate devices in nanoscale CMOS.
Microelectron. Reliab., 2012
2011
Analysis of Power Consumption and Linearity in Capacitive Digital-to-Analog Converters Used in Successive Approximation ADCs.
IEEE Trans. Circuits Syst. I Regul. Pap., 2011
Microelectron. J., 2011
IEICE Electron. Express, 2011
An optimization method for NBTI-aware design of domino logic circuits in nano-scale CMOS.
IEICE Electron. Express, 2011
Analysis and Design of Tunable Amplifiers for Implantable Neural Recording Applications.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2011
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
2010
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
A digital background correction technique combined with DWA for DAC mismatch errors in multibit ΣΔ ADCs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Linearity enhancement in Digital-to-Analog Converters using a modified decoding architecture.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Low-dropout voltage reference: An approach to buffered architectures with low sensitivity.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
2009
IEEE Trans. Circuits Syst. II Express Briefs, 2009
An Ultra-low-power 10-Bit 100-kS/s Successive-approximation Analog-to-digital Converter.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009
Proceedings of the 16th IEEE International Conference on Electronics, 2009
Proceedings of the 16th IEEE International Conference on Electronics, 2009
2008
On the Power Efficiency of cascode Compensation over Miller Compensation in Two-Stage Operational amplifiers.
J. Circuits Syst. Comput., 2008
Design of high-speed two-stage cascode-compensated operational amplifiers based on settling time and open-loop parameters.
Integr., 2008
IEICE Electron. Express, 2008
IEICE Electron. Express, 2008
Proceedings of the 2008 IEEE International Symposium on System-on-Chip, 2008
Simulation-equation-based methodology for design of CMOS amplifiers using Geometric Programming.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008
2007
Design of Two-Stage Miller-Compensated Amplifiers Based on an Optimized Settling Model.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007
Ultra-Low-Voltage, Low-Power, High-Speed Operational Amplifiers Using Body-Driven Gain-Boosting Technique.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
A Capacitor Mismatch- and Nonlinearity-Insensitive 1.5-bit Residue Stage for Pipelined ADCs.
Proceedings of the 14th IEEE International Conference on Electronics, 2007
Body-Driven Enhanced-Impedance Current Source: An Approach to the Implementation of Low-Voltage Current-Steering D/A Converters.
Proceedings of the 14th IEEE International Conference on Electronics, 2007
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007
2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Folded-current-steering DAC: an approach to low-voltage high-speed high-resolution D/A converters.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
A low-power CMOS Gm-C filter for wireless receiver applications with on-chip automatic tuning system.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Proceedings of the 13th IEEE International Conference on Electronics, 2006
2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
2004
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
A 12-bit 40MSPS 3.3-V 56-mW pipelined A/D convereter in 0.25-µm CMOS [convereter read converter].
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
Proceedings of the 2004 Design, 2004
2003
Low-power design techniques for low-voltage fast-settling operational amplifiers in switched-capacitor applications.
Integr., 2003
A low-power design methodology for high-resolution pipelined analog-to-digital converters.
Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003
A 1-V 1-mW high-speed class AB operational amplifier for high-speed low power pipelined A/D converters using "Slew Boost" technique.
Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003
A new architecture for rail-to-rail input constant-gm CMOS operational transconductance amplifiers.
Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003
An analytical approach to the estimation of the spurious-free dynamic range in pipeline A/D converters.
Proceedings of the 2003 10th IEEE International Conference on Electronics, 2003
Proceedings of the 2003 10th IEEE International Conference on Electronics, 2003
A 1.5-V 12-bit 75M-samples/s fully-differential low-power sample-and-hold amplifier in 0.25-μm CMOS.
Proceedings of the 2003 10th IEEE International Conference on Electronics, 2003
A Statistical Approach to Estimate the Dynamic Non-Linearity Parameters of Pipeline ADCs.
Proceedings of the 2003 International Conference on Computer-Aided Design, 2003
Proceedings of the 2003 International Conference on Computer-Aided Design, 2003
An analytical approach to the estimation of dynamic non-linearity parameters in pipeline A/D converters.
Proceedings of the ESSCIRC 2003, 2003