Mohammad Yavari
Orcid: 0000-0003-2007-2979
According to our database1,
Mohammad Yavari
authored at least 99 papers
between 2002 and 2024.
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Bibliography
2024
A Wide Dynamic Range CMOS Differential Rectifier for Radio Frequency Energy Harvesting Systems.
Circuits Syst. Signal Process., May, 2024
IEEE Trans. Circuits Syst. II Express Briefs, January, 2024
2023
0.5-V Nano-Power Shadow Sinusoidal Oscillator Using Bulk-Driven Multiple-Input Operational Transconductance Amplifier.
Sensors, February, 2023
2022
IEEE Trans. Circuits Syst. II Express Briefs, 2022
IEEE Trans. Circuits Syst. II Express Briefs, 2022
A push-pull FVF based LDO voltage regulator with slew rate enhancement at the gate of power transistor.
Microelectron. J., 2022
A front-end amplifier with tunable bandwidth and high value pseudo resistor for neural recording implants.
Microelectron. J., 2022
A Fully-Differential Chopper Capacitively-Coupled Amplifier with High Input Impedance for Closed-Loop Neural Recording.
Circuits Syst. Signal Process., 2022
2021
IEEE Trans. Circuits Syst. II Express Briefs, 2021
Restructuring hierarchical capacitated facility location problem with extended coverage radius under uncertainty.
Oper. Res., 2021
Circuits Syst. Signal Process., 2021
2020
A 56-to-66 GHz CMOS Low-Power Phased-Array Receiver Front-End With Hybrid Phase Shifting Scheme.
IEEE Trans. Circuits Syst., 2020
Semi-permutation-based genetic algorithm for order acceptance and scheduling in two-stage assembly problem.
Neural Comput. Appl., 2020
Shifting the sampled input signal in successive approximation register analog-to-digital converters to reduce the digital-to-analog converter switching energy and area.
Int. J. Circuit Theory Appl., 2020
Designing a resilient-green closed loop supply chain network for perishable products by considering disruption in both supply chain and power networks.
Comput. Chem. Eng., 2020
2019
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
Int. J. Circuit Theory Appl., 2019
A 17-to-24 GHz Low-Power Variable-Gain Low-Noise Amplifier in 65-nm CMOS for Phased-Array Receivers.
Circuits Syst. Signal Process., 2019
A Wideband High Linearity and Low-Noise CMOS Active Mixer Using the Derivative Superposition and Noise Cancellation Techniques.
Circuits Syst. Signal Process., 2019
Circuits Syst. Signal Process., 2019
Comput. Ind. Eng., 2019
2018
IEEE Trans. Circuits Syst. II Express Briefs, 2018
Statistics-Based Digital Background Calibration of Residue Amplifier Nonlinearity in Pipelined ADCs.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
IEEE Trans. Circuits Syst. II Express Briefs, 2018
A power conversion chain with an internally-set voltage reference and reusing the power receiver coil for wireless bio-implants.
Microelectron. J., 2018
An oscillatory noise-shaped quantizer for time-based continuous-time sigma-delta modulators.
Int. J. Circuit Theory Appl., 2018
2017
A Single Channel Split ADC Structure for Digital Background Calibration in Pipelined ADCs.
IEEE Trans. Very Large Scale Integr. Syst., 2017
IEEE Trans. Circuits Syst. I Regul. Pap., 2017
Integr., 2017
A power efficient buck-boost converter by reusing the coil inductor for wireless bio-implants.
Int. J. Circuit Theory Appl., 2017
A Simple Structure for MASH ΣΔ Modulators with Highly Reduced In-Band Quantization Noise.
Circuits Syst. Signal Process., 2017
2016
Using the Gate-Bulk Interaction and a Fundamental Current Injection to Attenuate IM3 and IM2 Currents in RF Transconductors.
IEEE Trans. Very Large Scale Integr. Syst., 2016
IEEE Trans. Circuits Syst. I Regul. Pap., 2016
Digital Calibration of Amplifier Finite DC Gain and Gain Bandwidth in MASH ΣΔ Modulators.
IEEE Trans. Circuits Syst. II Express Briefs, 2016
High-performance time-based continuous-time sigma-delta modulators using single-opamp resonator and noise-shaped quantizer.
Microelectron. J., 2016
An IIP3 enhancement technique for CMOS active mixers with a source-degenerated transconductance stage.
Microelectron. J., 2016
A wideband time-based continuous-time sigma-delta modulator with 2nd order noise-coupling based on passive elements.
Int. J. Circuit Theory Appl., 2016
Digital Background Calibration of Residue Amplifier Non-idealities in Pipelined ADCs.
Circuits Syst. Signal Process., 2016
2015
A Calibration Technique for Pipelined ADCs Using Self-Measurement and Histogram-Based Test Methods.
IEEE Trans. Circuits Syst. II Express Briefs, 2015
IEEE Trans. Circuits Syst. II Express Briefs, 2015
System level design and optimization of single-loop CT sigma-delta modulators for high resolution wideband applications.
Microelectron. J., 2015
A UWB CMOS low-noise amplifier with noise reduction and linearity improvement techniques.
Microelectron. J., 2015
A pseudo-differential current-reuse structure for opamp-sharing pipelined analog-to-digital converters.
Int. J. Circuit Theory Appl., 2015
Second-order intermodulation cancelation and conversion-gain enhancement techniques for CMOS active mixers.
Int. J. Circuit Theory Appl., 2015
2014
IEEE Trans. Very Large Scale Integr. Syst., 2014
A 10-Bit 0.5 V 100 KS/S SAR ADC with a New rail-to-rail Comparator for Energy Limited Applications.
J. Circuits Syst. Comput., 2014
Int. J. Circuit Theory Appl., 2014
2013
IEEE Trans. Circuits Syst. I Regul. Pap., 2013
Int. J. Circuit Theory Appl., 2013
2012
An Efficient Low-Power Sigma-Delta modulator for Multi-Standard Wireless Applications.
J. Circuits Syst. Comput., 2012
2011
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011
A linearization technique for active mixers in zero-IF receivers with inherent balun.
IEICE Electron. Express, 2011
A low power UWB very low noise amplifier using an improved noise reduction technique.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
A highly linear mixer with inherent balun using a new technique to remove common mode currents.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
A new digital background correction algorithm with non-precision calibration signals for pipelined ADCs.
Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems, 2011
Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems, 2011
Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems, 2011
Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems, 2011
2010
Active-Feedback Single Miller capacitor Frequency Compensation Techniques for Three-Stage amplifiers.
J. Circuits Syst. Comput., 2010
Low-voltage Double-Sampled Hybrid CT/DT sigmadelta modulator for Wideband Applications.
J. Circuits Syst. Comput., 2010
J. Circuits Syst. Comput., 2010
IEICE Electron. Express, 2010
IEICE Electron. Express, 2010
A digital background correction technique combined with DWA for DAC mismatch errors in multibit ΣΔ ADCs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
2009
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009
On the Design of a Less Jitter Sensitive NTF for NRZ Multi-bit Continuous-time DeltaSigma Modulators.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009
Multirate double-sampling hybrid CT/DT sigma-delta modulators for wideband applications.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009
Proceedings of the 16th IEEE International Conference on Electronics, 2009
Proceedings of the 16th IEEE International Conference on Electronics, 2009
A new architecture for low-power high-speed pipelined ADCs using double-sampling and opamp-sharing techniques.
Proceedings of the 16th IEEE International Conference on Electronics, 2009
Proceedings of the 19th European Conference on Circuit Theory and Design, 2009
2008
IEICE Electron. Express, 2008
A novel topology in reversed nested miller compensation using dual-active capacitance.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
2007
Accurate and simple modeling of amplifier dc gain nonlinearity in switched-capacitor circuits.
Proceedings of the 18th European Conference on Circuit Theory and Design, 2007
2006
IEEE Trans. Circuits Syst. II Express Briefs, 2006
Double-sampled cascaded sigma-delta modulator topologies for low oversampling ratios.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Double-sampling single-loop sigma-delta modulator topologies for broadband applications.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006
Systematic and optimal design of CMOS two-stage opamps with hybrid cascode compensation.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006
2005
IEEE Trans. Circuits Syst. II Express Briefs, 2005
IEICE Electron. Express, 2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
High-order single-loop double-sampling sigma-delta modulator topologies for broadband applications.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
A novel fully-differential class AB folded-cascode OTA for switched-capacitor applications.
Proceedings of the 12th IEEE International Conference on Electronics, 2005
2004
IEICE Electron. Express, 2004
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
An analytical model for the slewing behavior of CMOS two-stage operational transconductance amplifiers.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
2003
Low-voltage low-power fast-settling CMOS operational transconductance amplifiers for switched-capacitor applications.
Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003
A very low-voltage, low-power and high resolution sigma-delta modulator for digital audio in 0.25µm CMOS.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003
Proceedings of the 2003 10th IEEE International Conference on Electronics, 2003
A new compensation technique for two-stage CMOS operational transconductance amplifiers.
Proceedings of the 2003 10th IEEE International Conference on Electronics, 2003
Proceedings of the 2003 10th IEEE International Conference on Electronics, 2003
2002
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2002, 2002