Hamid Mahmoodi

According to our database1, Hamid Mahmoodi authored at least 94 papers between 2001 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Online presence:

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Bibliography

2019
RotaSYN: Rotary Traveling Wave Oscillator SYNthesizer.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

Security and Complexity Analysis of LUT-based Obfuscation: From Blueprint to Reality.
Proceedings of the International Conference on Computer-Aided Design, 2019

Deep RNN-Oriented Paradigm Shift through BOCANet: Broken Obfuscated Circuit Attack.
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019

On Custom LUT-based Obfuscation.
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019

2018
Programmable Gates Using Hybrid CMOS-STT Design to Prevent IC Reverse Engineering.
ACM Trans. Design Autom. Electr. Syst., 2018

Static Design of Spin Transfer Torques Magnetic Look Up Tables for ASIC Designs.
Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018

2016
Read static noise margin aging model considering SBD and BTI effects for FinFET SRAMs.
Microelectron. Reliab., 2016

Reliability analysis of spin transfer torque based look up tables under process variations and NBTI aging.
Microelectron. Reliab., 2016

Power and energy reduction of racetrack-based caches by exploiting shared shift operations.
Proceedings of the 2016 IFIP/IEEE International Conference on Very Large Scale Integration, 2016

Comparative analysis of hybrid Magnetic Tunnel Junction and CMOS logic circuits.
Proceedings of the 29th IEEE International System-on-Chip Conference, 2016

Preventing design reverse engineering with reconfigurable spin transfer torque LUT gates.
Proceedings of the 17th International Symposium on Quality Electronic Design, 2016

Comparative analysis of robustness of spin transfer torque based look up tables under process variations.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Dynamic single and Dual Rail spin transfer torque look up tables with enhanced robustness under CMOS and MTJ process variations.
Proceedings of the 34th IEEE International Conference on Computer Design, 2016

Hybrid STT-CMOS designs for reverse-engineering prevention.
Proceedings of the 53rd Annual Design Automation Conference, 2016

2014
Robust FinFET SRAM design based on dynamic back-gate voltage adjustment.
Microelectron. Reliab., 2014

Multi-level wordline driver for robust SRAM design in nano-scale CMOS technology.
Microelectron. J., 2014

Resistive Computation: A Critique.
IEEE Comput. Archit. Lett., 2014

Reconfigurable STT-NV LUT-based functional units to improve performance in general-purpose processors.
Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014

Exploiting STT-NV technology for reconfigurable, high performance, low power, and low temperature functional unit design.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013
An analytical model for read static noise margin including soft oxide breakdown, negative and positive bias temperature instabilities.
Microelectron. Reliab., 2013

Domino logic designs for high-performance and leakage-tolerant applications.
Integr., 2013

2012
Impacts of NBTI/PBTI on performance of domino logic circuits with high-k metal-gate devices in nanoscale CMOS.
Microelectron. Reliab., 2012

Modeling read SNM considering both soft oxide breakdown and negative bias temperature instability.
Microelectron. Reliab., 2012

Reliability enhancement of power gating transistor under time dependent dielectric breakdown.
Proceedings of the 20th IEEE/IFIP International Conference on VLSI and System-on-Chip, 2012

Impact of technology scaling on performance of domino logic in nano-scale CMOS.
Proceedings of the 20th IEEE/IFIP International Conference on VLSI and System-on-Chip, 2012

Impact of transistor aging effects on sense amplifier reliability in nano-scale CMOS.
Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

Flip-flop design using novel pulse generation technique.
Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

2011
Impact of NBTI on performance of domino logic circuits in nano-scale CMOS.
Microelectron. J., 2011

An optimization method for NBTI-aware design of domino logic circuits in nano-scale CMOS.
IEICE Electron. Express, 2011

Comparative BTI reliability analysis of SRAM cell designs in nano-scale CMOS technology.
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

Analysis of reliability of flip-flops under transistor aging effects in nano-scale CMOS technology.
Proceedings of the IEEE 29th International Conference on Computer Design, 2011

Multi-level wordline driver for low power SRAMs in nano-scale CMOS technology.
Proceedings of the IEEE 29th International Conference on Computer Design, 2011

Comparative analysis of copper and CNT interconnects for H-tree clock distribution.
Proceedings of the IEEE 29th International Conference on Computer Design, 2011

Low-Power and Variation-Tolerant Memory Design.
Proceedings of the Low-Power Variation-Tolerant Design in Nanometer Silicon, 2011

2010
Energy-efficient Hardware Architecture and VLSI Implementation of a Polyphase Channelizer with Applications to Subband Adaptive Filtering.
J. Signal Process. Syst., 2010

Low-overhead <i>F</i><sub><i>max</i></sub> calibration at multiple operating points using delay-sensitivity-based path selection.
ACM Trans. Design Autom. Electr. Syst., 2010

Postsilicon Adaptation for Low-Power SRAM under Process Variation.
IEEE Des. Test Comput., 2010

Thermal estimation for accurate estimation of impact of BTI aging effects on nano-scale SRAM circuits.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010

Comparison of performance parameters of SRAM designs in 16nm CMOS and CNTFET technologies.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010

New SRAM design using body bias technique for ultra low power applications.
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

Reliability analysis of power gated SRAM under combined effects of NBTI and PBTI in nano-scale CMOS.
Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

Data-dependant sense-amplifier flip-flop for low power applications.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

2009
Ultra Low-Power Clocking Scheme Using Energy Recovery and Clock Gating.
IEEE Trans. Very Large Scale Integr. Syst., 2009

Improved write margin 6T-SRAM for low supply voltage applications.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2009, 2009

Full-custom design project for digital VLSI and IC design courses using synopsys generic 90nm CMOS library.
Proceedings of the IEEE International Conference on Microelectronic Systems Education, 2009

Virtual Age: Enabling Technologies and Trends.
Proceedings of the Sixth International Conference on Information Technology: New Generations, 2009

New subthreshold concepts in 65nm CMOS technology.
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

Ultra Low Power Full Adder Topologies.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

2008
Reduction of Parametric Failures in Sub-100-nm SRAM Array Using Body Bias.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

A Low-Power SRAM Using Bit-Line Charge-Recycling.
IEEE J. Solid State Circuits, 2008

Arbitrary Two-Pattern Delay Testing Using a Low-Overhead Supply Gating Technique.
J. Electron. Test., 2008

65NM sub-threshold 11T-SRAM for ultra low voltage applications.
Proceedings of the 21st Annual IEEE International SoC Conference, SoCC 2008, 2008

Session 8 - Characterization and test methods for device variability in nanoscale technologies.
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

2007
Modeling and Circuit Synthesis for Independently Controlled Double Gate FinFET Devices.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Design of a Process Variation Tolerant Self-Repairing SRAM for Yield Enhancement in Nanoscaled CMOS.
IEEE J. Solid State Circuits, 2007

Strain Silicon Optimization for Memory and Logic in Nano-Scale CMOS.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

A low-power SRAM using bit-line charge-recycling technique.
Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007

Clock Gating and Negative Edge Triggering for Energy Recovery Clock.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Low-overhead design technique for calibration of maximum frequency at multiple operating points.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

2006
A novel high-performance and robust sense amplifier using independent gate control in sub-50-nm double-gate MOSFET.
IEEE Trans. Very Large Scale Integr. Syst., 2006

Novel Low-Overhead Operand Isolation Techniques for Low-Power Datapath Synthesis.
IEEE Trans. Very Large Scale Integr. Syst., 2006

Robust Sense Amplifier Design under Random Dopant Fluctuations in Nano-Scale CMOS Technologies.
Proceedings of the 2006 IEEE International SOC Conference, Austin, Texas, USA, 2006

Low power synthesis of dynamic logic circuits using fine-grained clock gating.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Low-overhead design of soft-error-tolerant scan flip-flops with enhanced-scan capability.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

2005
Efficient testing of SRAM with optimized march sequences and a novel DFT technique for emerging failures due to process variations.
IEEE Trans. Very Large Scale Integr. Syst., 2005

Low-power scan design using first-level supply gating.
IEEE Trans. Very Large Scale Integr. Syst., 2005

A process-tolerant cache architecture for improved yield in nanoscale technologies.
IEEE Trans. Very Large Scale Integr. Syst., 2005

Modeling of failure probability and statistical design of SRAM array for yield enhancement in nanoscaled CMOS.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

Modeling and Testing of SRAM for New Failure Mechanisms Due to Process Variations in Nanoscale CMOS.
Proceedings of the 23rd IEEE VLSI Test Symposium (VTS 2005), 2005

Dual-Edge Triggered Static Pulsed Flip-Flops.
Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

Reliable and self-repairing SRAM in nano-scale technologies using leakage and delay monitoring.
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

A leakage control system for thermal stability during burn-in test.
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

Design of High Performance Sense Amplifier Using Independent Gate Control in sub-50nm Double-Gate MOSFET.
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

Power Reduction in Test-Per-Scan BIST with Supply Gating and Efficient Scan Partitioning.
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

Pre-capturing static pulsed flip-flops.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Process Variation Tolerant Online Current Monitor for Robust Systems.
Proceedings of the 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 2005

Double-gate SOI devices for low-power and high-performance applications.
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

A high speed and leakage-tolerant domino logic for high fan-in gates.
Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005

Energy recovery clocked dynamic logic.
Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005

A Novel Low-overhead Delay Testing Technique for Arbitrary Two-Pattern Test Application.
Proceedings of the 2005 Design, 2005

A novel synthesis approach for active leakage power reduction using dynamic supply gating.
Proceedings of the 42nd Design Automation Conference, 2005

Leakage Current Based Stabilization Scheme for Robust Sense-Amplifier Design for Yield Enhancement in Nano-scale SRAM.
Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

2004
Diode-footed domino: a leakage-tolerant high fan-in dynamic circuit design style.
IEEE Trans. Circuits Syst. I Regul. Pap., 2004

Data-retention flip-flops for power-down applications.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Dual-edge triggered level converting flip-flops.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

A Novel Low-Power Scan Design Technique Using Supply Gating.
Proceedings of the 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 2004

Statistical design and optimization of SRAM cell for yield enhancement.
Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

Hardware architecture and VLSI implementation of a low-power high-performance polyphase channelizer with applications to subband adaptive filtering.
Proceedings of the 2004 IEEE International Conference on Acoustics, 2004

First Level Hold: A Novel Low-Overhead Delay Fault Testing Technique.
Proceedings of the 19th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2004), 2004

Estimation of delay variations due to random-dopant fluctuations in nano-scaled CMOS circuits.
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004

2003
Energy recovery clocking scheme and flip-flops for ultra low-energy applications.
Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003

2002
Leakage Current in Deep-Submicron CMOS Circuits.
J. Circuits Syst. Comput., 2002

High performance and low power FIR filter design based on sharing multiplication.
Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002

2001
Efficient power clock generation for adiabatic logic.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001


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