Ricardo Pannain

Orcid: 0000-0002-0210-0908

According to our database1, Ricardo Pannain authored at least 8 papers between 1998 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2023
DONUTS: An efficient method for checkpointing in non-volatile memories.
Concurr. Comput. Pract. Exp., 2023

Using Logging-on-Write to Improve Non-Volatile Memory Checkpoints via Processing-in-Memory.
Proceedings of the 35th IEEE International Symposium on Computer Architecture and High Performance Computing, 2023

2020
Bringing Energy Information to the Instruction Set.
Proceedings of the X Brazilian Symposium on Computing Systems Engineering, 2020

2009
SPARC16: A New Compression Approach for the SPARC Architecture.
Proceedings of the 21st International Symposium on Computer Architecture and High Performance Computing, 2009

2000
Expression-tree-based algorithms for code compression on embedded RISC architectures.
IEEE Trans. Very Large Scale Integr. Syst., 2000

1999
Compressão de codigo de programa usando fatoração de operandos.
PhD thesis, 1999

Compressed Code Execution on DSP Architectures.
Proceedings of the 12th International Symposium on System Synthesis, 1999

1998
Code Compression Based on Operand Factorization.
Proceedings of the 31st Annual IEEE/ACM International Symposium on Microarchitecture, 1998


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