Paulo Centoducatte

According to our database1, Paulo Centoducatte authored at least 20 papers between 1998 and 2012.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2012
ACCGen: An Automatic ArchC Compiler Generator.
Proceedings of the IEEE 24th International Symposium on Computer Architecture and High Performance Computing, 2012

2011
Using multiple abstraction levels to speedup an MPSoC virtual platform simulator.
Proceedings of the 22nd IEEE International Symposium on Rapid System Prototyping, 2011

2010
STM versus lock-based systems: an energy consumption perspective.
Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010

2009
Characterizing the Energy Consumption of Software Transactional Memory.
IEEE Comput. Archit. Lett., 2009

On the energy-efficiency of software transactional memory.
Proceedings of the 22st Annual Symposium on Integrated Circuits and Systems Design: Chip on the Dunes, 2009

SPARC16: A New Compression Approach for the SPARC Architecture.
Proceedings of the 21st International Symposium on Computer Architecture and High Performance Computing, 2009

2008
An open-source binary utility generator.
ACM Trans. Design Autom. Electr. Syst., 2008

A Software Transactional Memory System for an Asymmetric Processor Architecture.
Proceedings of the 20th International Symposium on Computer Architecture and High Performance Computing, 2008

2007
A Flexible Platform Framework for Rapid Transactional Memory Systems Prototyping and Evaluation.
Proceedings of the 18th IEEE International Workshop on Rapid System Prototyping (RSP 2007), 2007

Automatic Retargeting of Binary Utilities for Embedded Code Generation.
Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007

2005
Design of a decompressor engine on a SPARC processor.
Proceedings of the 18th Annual Symposium on Integrated Circuits and Systems Design, 2005

Extending the ArchC Language for Automatic Generation of Assemblers.
Proceedings of the 17th Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2005), 2005

2004
Teaching computer architecture using an architecture description language.
Proceedings of the 2004 workshop on Computer architecture education, 2004

Multi-Profile Instruction Based Compression.
Proceedings of the 16th Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2004), 2004

Multi-profile based code compression.
Proceedings of the 41th Design Automation Conference, 2004

2003
Mixed static/dynamic profiling for dictionary based code compression.
Proceedings of the 2003 International Symposium on System-on-Chip, 2003

2001
Tailoring pipeline bypassing and functional unit mapping to application in clustered VLIW architectures.
Proceedings of the 2001 International Conference on Compilers, 2001

2000
Expression-tree-based algorithms for code compression on embedded RISC architectures.
IEEE Trans. Very Large Scale Integr. Syst., 2000

1999
Compressed Code Execution on DSP Architectures.
Proceedings of the 12th International Symposium on System Synthesis, 1999

1998
Code Compression Based on Operand Factorization.
Proceedings of the 31st Annual IEEE/ACM International Symposium on Microarchitecture, 1998


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