Richard L. Walke

According to our database1, Richard L. Walke authored at least 13 papers between 1994 and 2012.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2012
IP-XACT extensions for IP interoperability guarantees and software model generation.
Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

2006
Multidimensional DSP Core Synthesis for FPGA.
J. VLSI Signal Process., 2006

2005
Rapid generation of hardware functionality in heterogeneous platforms [FPGA implementation applications].
Proceedings of the 2005 IEEE International Conference on Acoustics, 2005

2004
Embedded Context Aware Hardware Component Generation for Dataflow System Exploration.
Proceedings of the Computer Systems: Architectures, 2004

2003
Design of a parameterizable silicon intellectual property core for QR-based RLS filtering.
IEEE Trans. Very Large Scale Integr. Syst., 2003

Generic SoC QR array processor for adaptive beamforming.
IEEE Trans. Circuits Syst. II Express Briefs, 2003

2002
Compilation From Matlab to Process Networks Realized in FPGA.
Des. Autom. Embed. Syst., 2002

Preface.
Des. Autom. Embed. Syst., 2002

2001
Generic scheduling methods for a linear QR array SoC processor.
Proceedings of the IEEE International Conference on Acoustics, 2001

2000
Linear QR Architecture for a Single Chip Adaptive Beamformer.
J. VLSI Signal Process., 2000

Online CORDIC algorithm and VLSI architecture for implementing QR-array processors.
IEEE Trans. Signal Process., 2000

1999
Novel mapping of a linear QR architecture.
Proceedings of the 1999 IEEE International Conference on Acoustics, 1999

1994
A high performance IIR filter chip and its evaluation system.
Proceedings of the International Conference on Application Specific Array Processors, 1994


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