Roger F. Woods
According to our database^{1},
Roger F. Woods
authored at least 127 papers
between 1989 and 2019.
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Bibliography
2019
An Investigation of Using LoopBack Mechanism for Channel Reciprocity Enhancement in Secret Key Generation.
IEEE Trans. Mob. Comput., 2019
FPGABased Processor Acceleration for Image Processing Applications.
J. Imaging, 2019
Evaluation of FPGA Partitioning Schemes for Time and Space Sharing of Heterogeneous Tasks.
Proceedings of the Applied Reconfigurable Computing  15th International Symposium, 2019
2018
NanoStreams: A Microserver Architecture for RealTime Analytics on Fast Data Streams.
IEEE Trans. MultiScale Computing Systems, 2018
Security Optimization of Exposure RegionBased Beamforming With a Uniform Circular Array.
IEEE Trans. Communications, 2018
Opportunistic NonOrthogonal Multiple Access Scheme with Unreliable Wireless Backhauls.
Proceedings of the 29th IEEE Annual International Symposium on Personal, 2018
A Bayesian network based learning system for modelling faults in largescale manufacturing.
Proceedings of the IEEE International Conference on Industrial Technology, 2018
Facilitating Easier Access to FPGAs in the Heterogeneous Cloud Ecosystems.
Proceedings of the 28th International Conference on Field Programmable Logic and Applications, 2018
Exploring Functional Acceleration of OpenCL on FPGAs and GPUs Through PlatformIndependent Optimizations.
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2018
2017
FPGABased SoftCore Processors for Image Processing Applications.
Signal Processing Systems, 2017
Defining Spatial Secrecy Outage Probability for Exposure RegionBased Beamforming.
IEEE Trans. Wireless Communications, 2017
Design of an OFDM Physical Layer Encryption Scheme.
IEEE Trans. Vehicular Technology, 2017
On the Key Generation From Correlated Wireless Channels.
IEEE Communications Letters, 2017
Securing Wireless Communications of the Internet of Things from the Physical Layer, An Overview.
Entropy, 2017
Securing Wireless Communications of the Internet of Things from the Physical Layer, An Overview.
CoRR, 2017
2016
Efficient Key Generation by Exploiting Randomness From Channel Responses of Individual OFDM Subcarriers.
IEEE Trans. Communications, 2016
Defining Spatial Security Outage Probability for Exposure Region Based Beamforming.
CoRR, 2016
Experimental Study on Key Generation for Physical Layer Security in Wireless Communications.
IEEE Access, 2016
Key Generation From Wireless Channels: A Review.
IEEE Access, 2016
Experimental study on channel reciprocity in wireless key generation.
Proceedings of the 17th IEEE International Workshop on Signal Processing Advances in Wireless Communications, 2016
Runtime support for adaptive power capping on heterogeneous SoCs.
Proceedings of the International Conference on Embedded Computer Systems: Architectures, 2016
NanoStreams: Codesigned microservers for edge analytics in real time.
Proceedings of the International Conference on Embedded Computer Systems: Architectures, 2016
Proposing the Deep Dynamic Bayesian Network as a Future Computer Based Medical System.
Proceedings of the 29th IEEE International Symposium on ComputerBased Medical Systems, 2016
FPGA SoftCore Processors, Compiler and Hardware Optimizations Validated Using HOG.
Proceedings of the Applied Reconfigurable Computing  12th International Symposium, 2016
On spatial security outage probability derivation of exposure region based beamforming with randomly located eavesdroppers.
Proceedings of the 51st Asilomar Conference on Signals, Systems, and Computers, 2016
On spatial security outage probability derivation of exposure region based beamforming with randomly located eavesdroppers.
Proceedings of the 50th Asilomar Conference on Signals, Systems and Computers, 2016
2015
An effective key generation system using improved channel reciprocity.
Proceedings of the 2015 IEEE International Conference on Acoustics, 2015
Verification of Key Generation from Individual OFDM Subcarrier's Channel Response.
Proceedings of the 2015 IEEE Globecom Workshops, San Diego, CA, USA, December 610, 2015, 2015
2014
IPPro: FPGA based image processing processor.
Proceedings of the 2014 IEEE Workshop on Signal Processing Systems, 2014
Histogram of oriented gradients front end processing: An FPGA based processor approach.
Proceedings of the 2014 IEEE Workshop on Signal Processing Systems, 2014
Creating secure wireless regions using configurable beamforming.
Proceedings of the 25th IEEE Annual International Symposium on Personal, 2014
Secure key generation from OFDM subcarriers' channel responses.
Proceedings of the 2014 IEEE GLOBECOM Workshops, Austin, TX, USA, December 812, 2014, 2014
Power modelling and capping for heterogeneous ARM/FPGA SoCs.
Proceedings of the 2014 International Conference on FieldProgrammable Technology, 2014
Investigation of secure wireless regions using configurable beamforming on WARP.
Proceedings of the 48th Asilomar Conference on Signals, Systems and Computers, 2014
Dataflow toolset for softcore processors on FPGA for image processing applications.
Proceedings of the 48th Asilomar Conference on Signals, Systems and Computers, 2014
2013
Power Efficient, FPGA Implementations of Transform Algorithms for RadarBased Digital Receiver Applications.
IEEE Trans. Industrial Informatics, 2013
Optimization of Weighted Finite State Transducer for Speech Recognition.
IEEE Trans. Computers, 2013
Implementation of selective packet destruction on wireless openaccess research platform.
Proceedings of the 2013 Asilomar Conference on Signals, 2013
2012
An OnDemand Queue Management Architecture for a Programmable Traffic Manager.
IEEE Trans. VLSI Syst., 2012
Preface  ARC.
Microprocessors and Microsystems  Embedded Hardware Design, 2012
Novel Application of Genetic Sequencing Algorithms to Optimization of Hardware Resource Sharing for DSP.
Proceedings of the 23rd IEEE International Conference on ApplicationSpecific Systems, 2012
Session TA5b: Computer arithmetic accelerators for signal processing.
Proceedings of the Conference Record of the Forty Sixth Asilomar Conference on Signals, 2012
2011
RealValued FixedComplexity Sphere Decoder for High Dimensional QAMMIMO Systems.
IEEE Trans. Signal Processing, 2011
A Scalable and Programmable Modular Traffic Manager Architecture.
TRETS, 2011
FPGA Implementation of a Pipelined Gaussian Calculation for HMMBased Large Vocabulary Speech Recognition.
Int. J. Reconfig. Comp., 2011
Low power field programmable gate array implementation of fast digital signal processing algorithms: characterisation and manipulation of data locality.
IET Computers & Digital Techniques, 2011
How Resistant are Sboxes to Power Analysis Attacks?
Proceedings of the 4th IFIP International Conference on New Technologies, 2011
A Pipeline Interleaved Heterogeneous SIMD Soft Processor Array Architecture for MIMOOFDM Detection.
Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2011
Design and implementation of a flexible Queue Manager for Next Generation Networks.
Proceedings of the Conference Record of the Forty Fifth Asilomar Conference on Signals, 2011
Session MA8b1: Computer arithmetic I.
Proceedings of the Conference Record of the Forty Fifth Asilomar Conference on Signals, 2011
2010
SoC Memory Hierarchy Derivation from Dataflow Graphs.
Signal Processing Systems, 2010
Guest Editorial ARC 2009.
TRETS, 2010
A Programmable Architecture for Layered Multimedia Streams in IPv6 Networks.
JNW, 2010
Design of a flexible highspeed FPGAbased flow monitor for next generation networks.
Proceedings of the 2010 International Conference on Embedded Computer Systems: Architectures, 2010
Differential Power Analysis of CAST128.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010
Security of AES Sbox designs to power analysis.
Proceedings of the 17th IEEE International Conference on Electronics, 2010
Adapting noisy speech models  Extended uncertainty decoding.
Proceedings of the IEEE International Conference on Acoustics, 2010
Random clock against differential power analysis.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010
Mapping Decidable Signal Processing Graphs into FPGA Implementations.
Proceedings of the Handbook of Signal Processing Systems, 2010
2009
Introduction to the Special Issue ARC'08.
TRETS, 2009
Replacing uncertainty decoding with subband reestimation for large vocabulary speech recognition in noise.
Proceedings of the INTERSPEECH 2009, 2009
A traffic manager for integrated queuing and scheduling of unicast and multicast IP traffic.
Proceedings of the 2009 International Conference on Telecommunications, 2009
An AttackResilent Sampling Mechanism for Integrated IP Flow Monitors.
Proceedings of the 29th IEEE International Conference on Distributed Computing Systems Workshops (ICDCS 2009 Workshops), 2009
2008
From Bit Level Systolic Arrays to HDTV Processor Chips.
Signal Processing Systems, 2008
Current Trends on Reconfigurable Computing.
Int. J. Reconfig. Comp., 2008
Power efficient dynamicrange utilisation for DSP on FPGA.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2008
MemoryCentric Hardware Synthesis from Dataflow Models.
Proceedings of the Embedded Computer Systems: Architectures, 2008
A realtime flow monitor architecture encompassing ondemand monitoring functions.
Proceedings of the IEEE/IFIP Network Operations and Management Symposium: Pervasive Management for Ubioquitous Networks and Services, 2008
Combining noise compensation and missingfeature decoding for large vocabulary speech recognition in noise.
Proceedings of the INTERSPEECH 2008, 2008
Novel percussive Instrument Design  Converting Mathematical Formulae into engaging Musical Instruments.
Proceedings of the 2008 International Computer Music Conference, 2008
Power efficient DSP datapath configuration methodology for FPGA.
Proceedings of the FPL 2008, 2008
QR Recursive Least Squares IP Core Example.
Proceedings of the 15th Annual IEEE International Conference and Workshop on Engineering of Computer Based Systems (ECBS 2008), 31 March, 2008
2007
Design Methodology for RealTime FPGABased Sound Synthesis.
IEEE Trans. Signal Processing, 2007
Rapid implementation and optimisation of DSP systems on FPGAcentric heterogeneous platforms.
Journal of Systems Architecture, 2007
Transforming Signal Processing Applications into Parallel Implementations.
EURASIP J. Adv. Sig. Proc., 2007
SOC Memory Hierarchy Derivation from Dataflow Graphs.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2007
Physical Models and Musical Controllers  Designing a Novel Electronic Percussion Instrument.
Proceedings of the Seventh International Conference on New Interfaces for Musical Expression, 2007
Soft IP core implementation of recursive least squares filter using only multplicative and additive operators.
Proceedings of the FPL 2007, 2007
2006
Multidimensional DSP Core Synthesis for FPGA.
VLSI Signal Processing, 2006
Hierarchical synthesis of complex DSP functions using IRIS.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2006
Providing InputOutput Throughput Guarantees in a Buffered Crossbar Switch.
Proceedings of the 11th IEEE Symposium on Computers and Communications (ISCC 2006), 2006
Muir Hardware Synthesis for Multimedia Applications.
Proceedings of the 2006 4th Workshop on Embedded Systems for RealTime Multimedia, 2006
From Bit Level Systolic Arrays to HDTV Processor Chips.
Proceedings of the 2006 IEEE International Conference on ApplicationSpecific Systems, 2006
2005
High Speed FPGABased Implementations of DelayedLMS Filters.
VLSI Signal Processing, 2005
Virtex FPGA implementation of a pipelined adaptive LMS predictor for electronic support measures receivers.
IEEE Trans. VLSI Syst., 2005
Rapid Implementation and Optimisation of DSP Systems on SoPC Heterogeneous Platforms.
Proceedings of the Embedded Computer Systems: Architectures, 2005
A Novel Packet Marking Function for RealTime Interactive MPEG4 Video Applications in a Differentiated Services Network.
Proceedings of the NETWORKING 2005: Networking Technologies, 2005
Programmable Network Functionality for Improved QoS of Interactive Video Traffic.
Proceedings of the Network Control and Engineering for QoS, 2005
Rapid generation of hardware functionality in heterogeneous platforms [FPGA implementation applications].
Proceedings of the 2005 IEEE International Conference on Acoustics, 2005
Implementation of finite difference schemes for the wave equation on FPGA.
Proceedings of the 2005 IEEE International Conference on Acoustics, 2005
FPGABased Hardware for Physical Modelling Sound Synthesis by Finite Difference Schemes.
Proceedings of the 2005 IEEE International Conference on FieldProgrammable Technology, 2005
FPGA Core Network Implementation and Optimization: A Case Study.
Proceedings of the 2005 IEEE International Conference on FieldProgrammable Technology, 2005
Parallel implementation of finite difference schemes for the plate equation on a FPGAbased multiprocessor array.
Proceedings of the 13th European Signal Processing Conference, 2005
2004
Guest Editorial: Field Programmable Logic.
VLSI Signal Processing, 2004
Highly efficient, limited range multipliers for LUTbased FPGA architectures.
IEEE Trans. VLSI Syst., 2004
LMS coefficient filtering for Timevarying chirped signals.
IEEE Trans. Signal Processing, 2004
Embedded Context Aware Hardware Component Generation for Dataflow System Exploration.
Proceedings of the Computer Systems: Architectures, 2004
2003
Design of a parameterizable silicon intellectual property core for QRbased RLS filtering.
IEEE Trans. VLSI Syst., 2003
Design Flow for Efficient FPGA Reconfiguration.
Proceedings of the Field Programmable Logic and Application, 13th International Conference, 2003
2002
FPGAbased systemlevel design framework based on the IRIS synthesis tool and System Generator.
Proceedings of the 2002 IEEE International Conference on FieldProgrammable Technology, 2002
Multiplierless Realization of a Polyphase Filter Using LUTbased FPGAs.
Proceedings of the FieldProgrammable Logic and Applications, 2002
Mapping MultiMode Circuits to LUTBased FPGA Using Embedded MUXes.
Proceedings of the 10th IEEE Symposium on FieldProgrammable Custom Computing Machines (FCCM 2002), 2002
2001
Development of a RunTime Reconfiguration System with Low Reconfiguration Overhead.
VLSI Signal Processing, 2001
Advances in adaptive signal processing: totally adaptive systems.
Annual Reviews in Control, 2001
Implementation of fixed DSP functions using the reduced coefficient multiplier.
Proceedings of the IEEE International Conference on Acoustics, 2001
Virtex Implementation of Pipelined Adaptive LMS Predictor in Electronic Support Measures Receiver.
Proceedings of the FieldProgrammable Logic and Applications, 2001
2000
Linear QR Architecture for a Single Chip Adaptive Beamformer.
VLSI Signal Processing, 2000
Multiplexer Based Reconfiguration for Virtex Multipliers.
Proceedings of the FieldProgrammable Logic and Applications, 2000
An Investigation of Reconfigurable Multipliers for Use in Adaptive Signal Processing.
Proceedings of the 8th IEEE Symposium on FieldProgrammable Custom Computing Machines (FCCM 2000), 2000
Tracking performance of momentum LMS algorithm for a chirped sinusoidal signal.
Proceedings of the 10th European Signal Processing Conference, 2000
1999
Novel mapping of a linear QR architecture.
Proceedings of the 1999 IEEE International Conference on Acoustics, 1999
A Virtual Hardware Handler for RTR Systems.
Proceedings of the 7th IEEE Symposium on FieldProgrammable Custom Computing Machines (FCCM '99), 1999
Accelerating RunTime Reconfiguration on FCCMs.
Proceedings of the 7th IEEE Symposium on FieldProgrammable Custom Computing Machines (FCCM '99), 1999
1998
Applying an XC6200 to RealTime Image Processing.
IEEE Design & Test of Computers, 1998
The impact of data characteristics and hardware topology on hardware selection for low power DSP.
Proceedings of the 1998 International Symposium on Low Power Electronics and Design, 1998
Fast Partial Reconfiguration for FCCMs.
Proceedings of the 6th IEEE Symposium on FieldProgrammable Custom Computing Machines (FCCM '98), 1998
The impact of data characteristics on hardware selection for lowpower DSP.
Proceedings of the 9th European Signal Processing Conference, 1998
1997
Architectural Synthesis of Digital Signal Processing Algorithms Using "IRIS".
VLSI Signal Processing, 1997
FPGA synthesis on the XC6200 using IRIS and Trianus/Hades (or from heaven to hell and back again).
Proceedings of the 5th IEEE Symposium on FieldProgrammable Custom Computing Machines (FCCM '97), 1997
1996
Architectural Synthesis and Efficient Circuit Implementation for Field Programmable Gate Arrays.
Proceedings of the FieldProgrammable Logic, 1996
Architectural Strategies for Implementing an Image Processing Algorithm on XC6000 FPGA.
Proceedings of the FieldProgrammable Logic, 1996
VLSI architectures for field programmable gate arrays: a case study.
Proceedings of the 4th IEEE Symposium on FPGAs for Custom Computing Machines (FCCM '96), 1996
A New FFT Architecture and Chip Design for Motion Compensation based on Phase Correlation.
Proceedings of the 1996 International Conference on ApplicationSpecific Systems, 1996
1994
A high performance IIR filter chip and its evaluation system.
Proceedings of the International Conference on Application Specific Array Processors, 1994
1991
Design of a Highly Pipelined 2nd Order IIR Filter Chip.
Proceedings of the VLSI 91, 1991
1990
Optimized bit level architectures for IIR filtering.
Proceedings of the 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors, 1990
1989
BitLevel systolic architectures for high performance IIR filtering.
VLSI Signal Processing, 1989