Ed F. Deprettere
According to our database1,
Ed F. Deprettere
authored at least 126 papers
between 1982 and 2013.
Collaborative distances:
Collaborative distances:
Awards
IEEE Fellow
IEEE Fellow 1996, "For contributions in algorithm and architecture design for adaptive signal processing.".
Timeline
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On csauthors.net:
Bibliography
2013
Proceedings of the Handbook of Signal Processing Systems, 2013
Proceedings of the Handbook of Signal Processing Systems, 2013
2012
Proceedings of the 2012 International Conference on Embedded Computer Systems: Architectures, 2012
2011
Proceedings of the IEEE 9th Symposium on Application Specific Processors, 2011
2010
Proceedings of the Handbook of Signal Processing Systems, 2010
2009
Proceedings of the Embedded Computer Systems: Architectures, 2009
Proceedings of the Embedded Computer Systems: Architectures, 2009
2008
Systematic and Automated Multiprocessor System Design, Programming, and Implementation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008
Int. J. Embed. Syst., 2008
Automated Integration of Dedicated Hardwired IP Cores in Heterogeneous MPSoCs Designed with ESPAM.
EURASIP J. Embed. Syst., 2008
Proceedings of the IEEE Workshop on Signal Processing Systems, 2008
Tool Integration and Interoperability Challenges of a System-Level Design Flow: A Case Study.
Proceedings of the Embedded Computer Systems: Architectures, 2008
Proceedings of the 45th Design Automation Conference, 2008
2007
Parameterized Looped Schedules for Compact Representation of Execution Sequences in DSP Hardware and Software Implementation.
IEEE Trans. Signal Process., 2007
Classifying interprocess communication in process network representation of nested-loop programs.
ACM Trans. Embed. Comput. Syst., 2007
EURASIP J. Adv. Signal Process., 2007
Efficient External Memory Interface for Multi-processor Platforms Realized on FPGA Chips.
Proceedings of the FPL 2007, 2007
A framework for rapid system-level exploration, synthesis, and programming of multimedia MP-SoCs.
Proceedings of the 5th International Conference on Hardware/Software Codesign and System Synthesis, 2007
2006
J. VLSI Signal Process., 2006
Efficient Automated Synthesis, Programing, and Implementation of Multi-Processor Platforms on FPGA Chips.
Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006
FPGA Implementation of a Prototype Hierarchical Control Network for Large-Scale Signal Processing Applications.
Proceedings of the Euro-Par 2006, Parallel Processing, 12th International Euro-Par Conference, Dresden, Germany, August 28, 2006
Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, 2006
Affine Nested Loop Programs and their Binary Parameterized Dataflow Graph Counterparts.
Proceedings of the 2006 IEEE International Conference on Application-Specific Systems, 2006
2005
J. VLSI Signal Process., 2005
Proceedings of the Embedded Computer Systems: Architectures, 2005
Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005
Modeling and FPGA Implementation of Applications Using Parameterized Process Networks with Non-Static Parameters.
Proceedings of the 13th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2005), 2005
Proceedings of the 16th IEEE International Conference on Application-Specific Systems, 2005
Proceedings of the 16th IEEE International Conference on Application-Specific Systems, 2005
2004
An Integer Linear Programming Approach to Classify the Communication in Process Networks.
Proceedings of the Software and Compilers for Embedded Systems, 8th International Workshop, 2004
Proceedings of the Computer Systems: Architectures, 2004
Proceedings of the Computer Systems: Architectures, 2004
Proceedings of the Computer Systems: Architectures, 2004
Proceedings of the 15th IEEE International Workshop on Rapid System Prototyping (RSP 2004), 2004
Proceedings of the Field Programmable Logic and Application, 2004
Proceedings of the 2004 Design, 2004
Proceedings of the 2004 International Conference on Compilers, 2004
A Hierarchical Classification Scheme to Derive Interprocess Communication in Process Networks.
Proceedings of the 15th IEEE International Conference on Application-Specific Systems, 2004
2003
J. VLSI Signal Process., 2003
IEEE Trans. Signal Process., 2003
Proceedings of the Field Programmable Logic and Application, 13th International Conference, 2003
Proceedings of the 2003 Design, 2003
Proceedings of the 1st IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2003
Proceedings of the 14th IEEE International Conference on Application-Specific Systems, 2003
2002
Des. Autom. Embed. Syst., 2002
Proceedings of the Embedded Processor Design Challenges: Systems, Architectures, Modeling, and Simulation, 2002
Proceedings of the Embedded Processor Design Challenges: Systems, Architectures, Modeling, and Simulation, 2002
Algorithmic transformation techniques for efficient exploration of alternative application instances.
Proceedings of the Tenth International Symposium on Hardware/Software Codesign, 2002
A Compile Time Based Approach for Solving Out-of-Order Communication in Kahn Process Networks.
Proceedings of the 13th IEEE International Conference on Application-Specific Systems, 2002
2001
A Methodology for Architecture Exploration of Heterogeneous Signal Processing Systems.
J. VLSI Signal Process., 2001
A unified algebraic transformation approach for parallel recursive and adaptive filtering and SVD algorithms.
IEEE Trans. Signal Process., 2001
Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001
Proceedings of the Ninth International Symposium on Hardware/Software Codesign, 2001
2000
J. VLSI Signal Process., 2000
Efficient implementations of pipelined CORDIC based IIR digital filters using fast orthonormal μ-rotations.
IEEE Trans. Signal Process., 2000
Annihilation-reordering look-ahead pipelined CORDIC-based RLS adaptive filters and their application to adaptive beamforming.
IEEE Trans. Signal Process., 2000
Proceedings of the IEEE International Conference on Acoustics, 2000
Compaan: deriving process networks from Matlab for embedded signal processing architectures.
Proceedings of the Eighth International Workshop on Hardware/Software Codesign, 2000
Proceedings of the 12th IEEE International Conference on Application-Specific Systems, 2000
1999
A Clustering Approach to Explore Grain-Sizes in the Definition of Processing Elements in Dataflow Architectures.
J. VLSI Signal Process., 1999
Derivation of parallel and pipelined orthogonal filter architectures via algorithm transformations.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999
1998
Efficient Partitioning of Algorithms for Long Convolutions and their Mapping onto Architectures.
J. VLSI Signal Process., 1998
Proceedings of the 5th International Conference on Spoken Language Processing, Incorporating The 7th Australian International Speech Science and Technology Conference, Sydney Convention Centre, Sydney, Australia, 30th November, 1998
Proceedings of the 1998 IEEE International Conference on Acoustics, 1998
Proceedings of the 1998 IEEE International Conference on Acoustics, 1998
Proceedings of the 1998 IEEE International Conference on Acoustics, 1998
Proceedings of the Sixth International Workshop on Hardware/Software Codesign, 1998
1997
Proceedings of the Fifth European Conference on Speech Communication and Technology, 1997
Proceedings of the 1997 IEEE International Conference on Acoustics, 1997
Proceedings of the 1997 IEEE International Conference on Acoustics, 1997
Proceedings of the 1997 International Conference on Application-Specific Systems, 1997
An Approach for Quantitative Analysis of Application-Specific Dataflow Architectures.
Proceedings of the 1997 International Conference on Application-Specific Systems, 1997
Proceedings of the 13th Symposium on Computer Arithmetic (ARITH-13 '97), 1997
1996
J. VLSI Signal Process., 1996
IEEE Signal Process. Lett., 1996
Proceedings of the 1996 IEEE International Conference on Acoustics, 1996
Proceedings of the 8th European Signal Processing Conference, 1996
Proceedings of the 1996 International Conference on Application-Specific Systems, 1996
1995
A parallel image-rendering algorithm and architecture based on ray tracing and radiosity shading.
Comput. Graph., 1995
On the derivation of parallel filter structures for adaptive eigenvalue and singular value decompositions.
Proceedings of the 1995 International Conference on Acoustics, 1995
1994
IEEE Trans. Signal Process., 1994
Signal Process., 1994
Is it Possible to achieve a Teraflop/s on a chip? From High Performance Algorithms to Architectures.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994
Proceedings of ICASSP '94: IEEE International Conference on Acoustics, 1994
Proceedings of the International Conference on Application Specific Array Processors, 1994
1993
Proceedings of the International Conference on Application-Specific Array Processors, 1993
Proceedings of the 11th Symposium on Computer Arithmetic, 29 June, 1993
1992
IEEE Trans. Signal Process., 1992
IEEE Trans. Circuits Syst. Video Technol., 1992
Proceedings of the EGGH92: Eurographics Workshop on Graphics Hardware 1992, 1992
1991
IEEE Trans. Signal Process., 1991
Efficient methods to compute azimuth and elevation in high resolution DOA estimation.
Proceedings of the 1991 International Conference on Acoustics, 1991
Proceedings of the conference on European design automation, 1991
Space Partitioning for Mapping Radiosity Computations onto a Pipelined Parallel Architecture (II).
Proceedings of the Rendering, 1991
Proceedings of the Application Specific Array Processors, 1991
Design and implementation of a floating-point quasi-systolic general purpose CORDIC rotator for high-rate parallel data and signal processing.
Proceedings of the 10th IEEE Symposium on Computer Arithmetic, 1991
1990
IEEE Micro, 1990
Real time application of the floating point pipeline CORDIC processor in massive-parallel pipelined DSP algorithms.
Proceedings of the 1990 International Conference on Acoustics, 1990
A New Space Partitioning for Mapping Computations of the Radiosity Method onto a Highly Pipelined Parallel Architecture.
Proceedings of the Rendering, 1990
Proceedings of the Application Specific Array Processors, 1990
Proceedings of the Application Specific Array Processors, 1990
1989
A systolic algorithm and architecture for solving sets of linear equations with multi-band coefficient matrix.
J. VLSI Signal Process., 1989
Vis. Comput., 1989
Proceedings of the Advances in Computer Graphics Hardware IV (Eurographics'89 Workshop), 1989
Proceedings of the 26th ACM/IEEE Design Automation Conference, 1989
1988
A class of analysis-by-synthesis predictive coders for high quality speech coding at rates between 4.8 and 16 kbit/s.
IEEE J. Sel. Areas Commun., 1988
Proceedings of the 15th Annual International Symposium on Computer Architecture, 1988
Converting sequential iterative algorithms to recurrent equations for automatic design of systolic arrays.
Proceedings of the IEEE International Conference on Acoustics, 1988
1987
Proceedings of the IEEE International Conference on Acoustics, 1987
1986
Regular-pulse excitation-A novel approach to effective and efficient multipulse coding of speech.
IEEE Trans. Acoust. Speech Signal Process., 1986
Design and VLSI Implementation of a Concurrent Solver for N-Coupled Least-Squares Fitting Problems.
IEEE J. Sel. Areas Commun., 1986
Proceedings of the IEEE International Conference on Acoustics, 1986
1985
Proceedings of the IEEE International Conference on Acoustics, 1985
1984
Proceedings of the IEEE International Conference on Acoustics, 1984
Proceedings of the IEEE International Conference on Acoustics, 1984
1983
Proceedings of the IEEE International Conference on Acoustics, 1983
1982
Proceedings of the IEEE International Conference on Acoustics, 1982