Rickard Holsmark

According to our database1, Rickard Holsmark authored at least 17 papers between 2003 and 2013.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2013
An Efficient Router Architecture and Its FPGA Prototyping to Support Junction Based Routing in NoC Platforms.
Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

2012
Junction based routing: a scalable technique to support source routing in large NoC platforms.
Proceedings of the Fifth International Workshop on Network on Chip Architectures, 2012

2011
An Abstraction to Support Design of Deadlock-free Routing Algorithms for Large and Hierarchical NoCs.
Proceedings of the 11th IEEE International Conference on Computer and Information Technology, 2011

Application-Specific Routing Algorithms for Low Power Network on Chip Design.
Proceedings of the Low Power Networks-on-Chip., 2011

2010
A Multi-level Routing Scheme and Router Architecture to Support Hierarchical Routing in Large Network on Chip Platforms.
Proceedings of the Euro-Par 2010 Parallel Processing Workshops, 2010

An Efficient Technique for In-order Packet Delivery with Adaptive Routing Algorithms in Networks on Chip.
Proceedings of the 13th Euromicro Conference on Digital System Design, 2010

2009
Region-Based Routing: A Mechanism to Support Efficient Routing Algorithms in NoCs.
IEEE Trans. Very Large Scale Integr. Syst., 2009

Application Specific Routing Algorithms for Networks on Chip.
IEEE Trans. Parallel Distributed Syst., 2009

HiRA: A methodology for deadlock free routing in hierarchical networks on chip.
Proceedings of the Third International Symposium on Networks-on-Chips, 2009

2008
Deadlock free routing algorithms for irregular mesh topology NoC systems with rectangular regions.
J. Syst. Archit., 2008

Design of Bandwidth Aware and Congestion Avoiding Efficient Routing Algorithms for Networks-on-Chip Platforms.
Proceedings of the Second International Symposium on Networks-on-Chips, 2008

2007
Corrections to Chen and Chiu's Fault Tolerant Routing Algorithm for Mesh Networks.
J. Inf. Sci. Eng., 2007

Exploiting Communication Concurrency for Efficient Deadlock Free Routing in Reconfigurable NoC Platforms.
Proceedings of the 21th International Parallel and Distributed Processing Symposium (IPDPS 2007), 2007

2006
A Method for Router Table Compression for Application Specific Routing in Mesh Topology NoC Architectures.
Proceedings of the Embedded Computer Systems: Architectures, 2006

Deadlock Free Routing Algorithms for Mesh Topology NoC Systems with Regions.
Proceedings of the Ninth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2006), 30 August, 2006

A methodology for design of application specific deadlock-free routing algorithms for NoC systems.
Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, 2006

2003
Modelling and Evaluation of a Network on Chip Architecture Using SDL.
Proceedings of the SDL 2003: System Design, 2003


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