José Flich
Orcid: 0000-0001-8581-6284Affiliations:
- Technical University of Valencia, Department of Computer Architecture, Spain
According to our database1,
José Flich
authored at least 181 papers
between 1998 and 2023.
Collaborative distances:
Collaborative distances:
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Bibliography
2023
Proceedings of the High Performance Computing, 2023
Proceedings of the 31st Euromicro International Conference on Parallel, 2023
An Open-Source FPGA Platform for Shared-Memory Heterogeneous Many-Core Architecture Exploration.
Proceedings of the 38th Conference on Design of Circuits and Integrated Systems, 2023
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
2022
Enabling dynamic and intelligent workflows for HPC, data analytics, and AI convergence.
Future Gener. Comput. Syst., 2022
Efficient Inference Of Image-Based Neural Network Models In Reconfigurable Systems With Pruning And Quantization.
Proceedings of the 2022 IEEE International Conference on Image Processing, 2022
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
The DeepHealth Toolkit: A Key European Free and Open-Source Software for Deep Learning and Computer Vision Ready to Exploit Heterogeneous HPC and Cloud Architectures.
Proceedings of the Technologies and Applications for Big Data Value, 2022
2021
UPR: deadlock-free dynamic network reconfiguration by exploiting channel dependency graph compatibility.
J. Supercomput., 2021
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
2020
Microprocess. Microsystems, 2020
HP-DCFNoC: High Performance Distributed Dynamic TDM Scheduler Based on DCFNoC Theory.
IEEE Access, 2020
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2020
SELENE: Self-Monitored Dependable Platform for High-Performance Safety-Critical Systems.
Proceedings of the 23rd Euromicro Conference on Digital System Design, 2020
2019
Guest Editors' Introduction: Emerging Networks-on-Chip Designs, Technologies, and Applications.
ACM J. Emerg. Technol. Comput. Syst., 2019
A Low-Latency and Flexible TDM NoC for Strong Isolation in Security-Critical Systems.
Proceedings of the 13th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2019
Proceedings of the 22nd Euromicro Conference on Digital System Design, 2019
Proceedings of the 56th Annual Design Automation Conference 2019, 2019
2018
IEEE Trans. Parallel Distributed Syst., 2018
Exploring manycore architectures for next-generation HPC systems through the MANGO approach.
Microprocess. Microsystems, 2018
Reliable power and time-constraints-aware predictive management of heterogeneous exascale systems.
Proceedings of the 18th International Conference on Embedded Computer Systems: Architectures, 2018
2017
IEEE Trans. Parallel Distributed Syst., 2017
Deeply Heterogeneous Many-Accelerator Infrastructure for HPC Architecture Exploration.
Proceedings of the Parallel Computing is Everywhere, 2017
Proceedings of the 2017 International Conference on High Performance Computing & Simulation, 2017
Proceedings of the Euromicro Conference on Digital System Design, 2017
2016
IEEE Trans. Parallel Distributed Syst., 2016
End-Point Congestion Filter for Adaptive Routing with Congestion-Insensitive Performance.
IEEE Comput. Archit. Lett., 2016
Proceedings of the Tenth IEEE/ACM International Symposium on Networks-on-Chip, 2016
Proceedings of the Tenth IEEE/ACM International Symposium on Networks-on-Chip, 2016
Increasing the Efficiency of Latency-Driven DVFS with a Smart NoC Congestion Management Strategy.
Proceedings of the 10th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2016
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
2015
Efficient and Cost-Effective Hybrid Congestion Control for HPC Interconnection Networks.
IEEE Trans. Parallel Distributed Syst., 2015
A Brief Comment on "A Complete Self-Testing and Self-Configuring NoC Infrastructure for Cost-Effective MPSoCs" [ACM Transactions on Embedded Computing Systems 12 (2013) Article 106].
ACM Trans. Embed. Comput. Syst., 2015
The fast evolving landscape of on-chip communication - Selected future challenges and research avenues.
Des. Autom. Embed. Syst., 2015
Area-efficient snoopy-aware NoC design for high-performance chip multiprocessor systems.
Comput. Electr. Eng., 2015
Proceedings of the 17th IEEE International Conference on High Performance Computing and Communications, 2015
On the Design of a Path-Setup Architecture for Exploiting Hybrid Photonic-Electronic NoCs.
Proceedings of the 2015 Workshop on Exploiting Silicon Photonics for Energy-Efficient High Performance Computing, 2015
Proceedings of the Euro-Par 2015: Parallel Processing Workshops, 2015
d<sup>2</sup>-LBDR: distance-driven routing to handle permanent failures in 2D mesh NOCs.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
Synergistic use of multiple on-chip networks for ultra-low latency and scalable distributed routing reconfiguration.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
Proceedings of the 18th IEEE International Conference on Computational Science and Engineering, 2015
2014
Path-Based Partitioning Methods for 3D Networks-on-Chip with Minimal Adaptive Routing.
IEEE Trans. Computers, 2014
IEEE Trans. Computers, 2014
Microprocess. Microsystems, 2014
Achieving balanced buffer utilization with a proper co-design of flow control and routing algorithm.
Proceedings of the Eighth IEEE/ACM International Symposium on Networks-on-Chip, 2014
Proceedings of the Eighth IEEE/ACM International Symposium on Networks-on-Chip, 2014
2013
An Effective and Feasible Congestion Management Technique for High-Performance MINs with Tag-Based Distributed Routing.
IEEE Trans. Parallel Distributed Syst., 2013
A complete self-testing and self-configuring NoC infrastructure for cost-effective MPSoCs.
ACM Trans. Embed. Comput. Syst., 2013
ACM Trans. Embed. Comput. Syst., 2013
NII Shonan Meet. Rep., 2013
J. Syst. Archit., 2013
IET Comput. Digit. Tech., 2013
Adaptive routing and Dynamic Frequency Scaling for NoC power-performance optimizations.
Proceedings of the 2013 23rd International Workshop on Power and Timing Modeling, 2013
An NoC and cache hierarchy substrate to address effective virtualization and fault-tolerance.
Proceedings of the 2013 Seventh IEEE/ACM International Symposium on Networks-on-Chip (NoCS), 2013
Optimizing the overhead for network-on-chip routing reconfiguration in parallel multi-core platforms.
Proceedings of the 2013 International Symposium on System on Chip, 2013
Proceedings of the 2013 IEEE International Symposium on Parallel & Distributed Processing, 2013
Proceedings of the 2013 IEEE International Symposium on Parallel & Distributed Processing, 2013
A fast algorithm for runtime reconfiguration to maximize the lifetime of nanoscale NoCs.
Proceedings of the 2013 Interconnection Network Architecture: On-Chip, Multi-Chip, 2013
Proceedings of the Euro-Par 2013: Parallel Processing Workshops, 2013
Proceedings of the Euro-Par 2013 Parallel Processing, 2013
Proceedings of the Euro-Par 2013: Parallel Processing Workshops, 2013
Proceedings of the Euro-Par 2013 Parallel Processing, 2013
2012
IEEE Trans. Parallel Distributed Syst., 2012
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012
J. Syst. Archit., 2012
J. Parallel Distributed Comput., 2012
Proceedings of the 2012 International Conference on Embedded Computer Systems: Architectures, 2012
Proceedings of the 20th Euromicro International Conference on Parallel, 2012
Proceedings of the 2012 Sixth IEEE/ACM International Symposium on Networks-on-Chip (NoCS), 2012
Proceedings of the 2012 Sixth IEEE/ACM International Symposium on Networks-on-Chip (NoCS), 2012
Proceedings of the 41st International Conference on Parallel Processing, 2012
Proceedings of the 2012 Interconnection Network Architecture, 2012
Heterogeneous network design for effective support of invalidation-based coherency protocols.
Proceedings of the 2012 Interconnection Network Architecture, 2012
Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012
Dynamic Last-Level Cache Allocation to Reduce Area and Power Overhead in Directory Coherence Protocols.
Proceedings of the Euro-Par 2012 Parallel Processing - 18th International Conference, 2012
Detecting Sharing Patterns in Industrial Parallel Applications for Embedded Heterogeneous Multicore Systems.
Proceedings of the Euro-Par 2012: Parallel Processing Workshops, 2012
2011
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011
Microprocess. Microsystems, 2011
J. Parallel Distributed Comput., 2011
OBQA: Smart and cost-efficient queue scheme for Head-of-Line blocking elimination in fat-trees.
J. Parallel Distributed Comput., 2011
Int. J. Parallel Program., 2011
Concurr. Comput. Pract. Exp., 2011
IEEE Comput. Archit. Lett., 2011
Proceedings of the NOCS 2011, 2011
Proceedings of The Tenth IEEE International Symposium on Networking Computing and Applications, 2011
Proceedings of the International Conference on Parallel Processing, 2011
Combining Congested-Flow Isolation and Injection Throttling in HPC Interconnection Networks.
Proceedings of the International Conference on Parallel Processing, 2011
Proceedings of the International Conference on Parallel Processing, 2011
Proceedings of the Fifth International Workshop on Interconnection Network Architecture, 2011
Proceedings of the 18th International Conference on High Performance Computing, 2011
Proceedings of the 14th Euromicro Conference on Digital System Design, 2011
HPC-Mesh: A Homogeneous Parallel Concentrated Mesh for Fault-Tolerance and Energy Savings.
Proceedings of the 2011 ACM/IEEE Symposium on Architectures for Networking and Communications Systems (ANCS), 2011
2010
IEEE Trans. Parallel Distributed Syst., 2010
Proceedings of the NOCS 2010, 2010
Proceedings of the NOCS 2010, 2010
Proceedings of the 24th IEEE International Symposium on Parallel and Distributed Processing, 2010
Cost-Effective Congestion Management for Interconnection Networks Using Distributed Deterministic Routing.
Proceedings of the 16th IEEE International Conference on Parallel and Distributed Systems, 2010
VCTlite: Towards an efficient implementation of virtual cut-through switching in on-chip networks.
Proceedings of the 2010 International Conference on High Performance Computing, 2010
Proceedings of the Euro-Par 2010 - Parallel Processing, 16th International Euro-Par Conference, Ischia, Italy, August 31, 2010
Proceedings of the 13th Euromicro Conference on Digital System Design, 2010
2009
IEEE Trans. Very Large Scale Integr. Syst., 2009
IEEE Trans. Parallel Distributed Syst., 2009
IET Comput. Digit. Tech., 2009
A performance evaluation of 2D-mesh, ring, and crossbar interconnects for chip multi-processors.
Proceedings of the Second International Workshop on Network on Chip Architectures, 2009
Proceedings of the 2008 IEEE International Symposium on System-on-Chip, 2009
Proceedings of the 2008 IEEE International Symposium on System-on-Chip, 2009
Proceedings of the Euro-Par 2009 Parallel Processing, 2009
2008
IEEE Trans. Computers, 2008
Scalable Comput. Pract. Exp., 2008
Proceedings of the ACM/IEEE Conference on High Performance Computing, 2008
Proceedings of the Second International Symposium on Networks-on-Chips, 2008
Proceedings of the 41st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-41 2008), 2008
Epoch-based reconfiguration: Fast, simple, and effective dynamic network reconfiguration.
Proceedings of the 22nd IEEE International Symposium on Parallel and Distributed Processing, 2008
Proceedings of the 2008 International Conference on Parallel Processing, 2008
FBICM: Efficient Congestion Management for High-Performance Networks Using Distributed Deterministic Routing.
Proceedings of the High Performance Computing, 2008
Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008
2007
Proceedings of the 2007 Workshop on Computer Architecture Education, 2007
Proceedings of the 15th Euromicro International Conference on Parallel, 2007
Region-Based Routing: An Efficient Routing Mechanism to Tackle Unreliable Hardware in Network on Chips.
Proceedings of the First International Symposium on Networks-on-Chips, 2007
RECN-IQ: A Cost-Effective Input-Queued Switch Architecture with Congestion Management.
Proceedings of the 2007 International Conference on Parallel Processing (ICPP 2007), 2007
Proceedings of the Euro-Par 2007, 2007
2006
IEEE Trans. Computers, 2006
IEEE Micro, 2006
Segment-based routing: an efficient fault-tolerant routing algorithm for meshes and tori.
Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), 2006
Proceedings of the 2006 International Conference on Parallel Processing (ICPP 2006), 2006
Proceedings of the 12th International Conference on Parallel and Distributed Systems, 2006
Proceedings of the 12th International Conference on Parallel and Distributed Systems, 2006
Towards a Cost-Effective Interconnection Network Architecture with QoS and Congestion Management Support.
Proceedings of the Euro-Par 2006, Parallel Processing, 12th International Euro-Par Conference, Dresden, Germany, August 28, 2006
Proceedings of the 2006 ACM/IEEE Symposium on Architecture for Networking and Communications Systems, 2006
2005
J. Parallel Distributed Comput., 2005
Studying the Effect of the Design Parameters on the Interconnection Network Performance in NOWs.
Proceedings of the 13th Euromicro Workshop on Parallel, 2005
Proceedings of the High-Performance Computing - 6th International Symposium, 2005
Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 2005
Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 2005
A New Scalable and Cost-Effective Congestion Management Strategy for Lossless Multistage Interconnection Networks.
Proceedings of the 11th International Conference on High-Performance Computer Architecture (HPCA-11 2005), 2005
Proceedings of the High Performance Embedded Architectures and Compilers, 2005
Proceedings of the Euro-Par 2005, Parallel Processing, 11th International Euro-Par Conference, Lisbon, Portugal, August 30, 2005
Proceedings of the Euro-Par 2005, Parallel Processing, 11th International Euro-Par Conference, Lisbon, Portugal, August 30, 2005
2004
IEEE Comput. Archit. Lett., 2004
IEEE Comput. Archit. Lett., 2004
A Cost-Effective Technique to Reduce HOL Blocking in Single-Stage and Multistage Switch Fabrics.
Proceedings of the 12th Euromicro Workshop on Parallel, 2004
Proceedings of the Network and Parallel Computing, IFIP International Conference, 2004
Proceedings of the 18th International Parallel and Distributed Processing Symposium (IPDPS 2004), 2004
Proceedings of the 33rd International Conference on Parallel Processing (ICPP 2004), 2004
Proceedings of the 10th International Conference on Parallel and Distributed Systems, 2004
Proceedings of the High Performance Computing, 2004
Proceedings of the High Performance Computing, 2004
2003
Applying In-Transit Buffers to Boost the Performance of Networks with Source Routing.
IEEE Trans. Computers, 2003
Proceedings of the 11th Euromicro Workshop on Parallel, 2003
Proceedings of the 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 2003
Proceedings of the 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 2003
Proceedings of the 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 2003
Proceedings of the 32nd International Conference on Parallel Processing (ICPP 2003), 2003
Low-Fragmentation Mapping Strategies for Linear Forwarding Tables in InfiniBand<sup>TM</sup>.
Proceedings of the Euro-Par 2003. Parallel Processing, 2003
2002
IEEE Trans. Parallel Distributed Syst., 2002
Proceedings of the 10th Euromicro Workshop on Parallel, 2002
Proceedings of the High Performance Computing, 4th International Symposium, 2002
Proceedings of the 16th International Parallel and Distributed Processing Symposium (IPDPS 2002), 2002
Proceedings of the 16th International Parallel and Distributed Processing Symposium (IPDPS 2002), 2002
Proceedings of the 31st International Conference on Parallel Processing (ICPP 2002), 2002
Proceedings of the Euro-Par 2002, 2002
2001
Improving Network Performance by Reducing Network Contention in Source-Based COWs with a Low Path-Computation Overhead.
Proceedings of the 15th International Parallel & Distributed Processing Symposium (IPDPS-01), 2001
Proceedings of the 15th International Parallel & Distributed Processing Symposium (IPDPS-01), 2001
Proceedings of the 2001 International Conference on Parallel Processing, 2001
2000
Combining In-Transit Buffers with Optimized Routing Schemes to Boost the Performance of Networks with Source Routing.
Proceedings of the High Performance Computing, Third International Symposium, 2000
Proceedings of the 14th International Parallel & Distributed Processing Symposium (IPDPS'00), 2000
Performance evaluation of a new routing strategy for irregular networks with source routing.
Proceedings of the 14th international conference on Supercomputing, 2000
Proceedings of the 2000 International Conference on Parallel Processing, 2000
1999
Performance Evaluation of Networks of Workstations with Hardware Shared Memory Model Using Execution-Driven Simulation.
Proceedings of the International Conference on Parallel Processing 1999, 1999
1998
Proceedings of the Computer Performance Evaluation: Modelling Techniques and Tools, 1998