Jose Flich

According to our database1, Jose Flich authored at least 174 papers between 1998 and 2022.

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Bibliography

2022
Enabling Dynamic and Intelligent Workflows for HPC, Data Analytics, and AI Convergence.
CoRR, 2022

2021
UPR: deadlock-free dynamic network reconfiguration by exploiting channel dependency graph compatibility.
J. Supercomput., 2021

Enforcing Predictability of Many-Cores With DCFNoC.
IEEE Trans. Computers, 2021

The RECIPE Approach to Challenges in Deeply Heterogeneous High Performance Systems.
CoRR, 2021

Improving the Robustness of Redundant Execution with Register File Randomization.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

From a FPGA Prototyping Platform to a Computing Platform: The MANGO Experience.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

2020
The RECIPE approach to challenges in deeply heterogeneous high performance systems.
Microprocess. Microsystems, 2020

TDSR: Transparent Distributed Segment-Based Routing.
CoRR, 2020

HP-DCFNoC: High Performance Distributed Dynamic TDM Scheduler Based on DCFNoC Theory.
IEEE Access, 2020

Distributed Training on a Highly Heterogeneous HPC System.
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2020

SELENE: Self-Monitored Dependable Platform for High-Performance Safety-Critical Systems.
Proceedings of the 23rd Euromicro Conference on Digital System Design, 2020

2019
Guest Editors' Introduction: Emerging Networks-on-Chip Designs, Technologies, and Applications.
ACM J. Emerg. Technol. Comput. Syst., 2019

A Low-Latency and Flexible TDM NoC for Strong Isolation in Security-Critical Systems.
Proceedings of the 13th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2019

Challenges in Deeply Heterogeneous High Performance Systems.
Proceedings of the 22nd Euromicro Conference on Digital System Design, 2019

DCFNoC: A Delayed Conflict-Free Time Division Multiplexing Network on Chip.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2018
PROSA: Protocol-Driven Network on Chip Architecture.
IEEE Trans. Parallel Distributed Syst., 2018

Exploring manycore architectures for next-generation HPC systems through the MANGO approach.
Microprocess. Microsystems, 2018

Reliable power and time-constraints-aware predictive management of heterogeneous exascale systems.
Proceedings of the 18th International Conference on Embedded Computer Systems: Architectures, 2018

2017
Path Setup for Hybrid NoC Architectures Exploiting Flooding and Standby.
IEEE Trans. Parallel Distributed Syst., 2017

Deeply Heterogeneous Many-Accelerator Infrastructure for HPC Architecture Exploration.
Proceedings of the Parallel Computing is Everywhere, 2017

ICARO-PAPM: Congestion Management with Selective Queue Power-Gating.
Proceedings of the 2017 International Conference on High Performance Computing & Simulation, 2017


2016
CUTBUF: Buffer Management and Router Design for Traffic Mixing in VNET-Based NoCs.
IEEE Trans. Parallel Distributed Syst., 2016

End-Point Congestion Filter for Adaptive Routing with Congestion-Insensitive Performance.
IEEE Comput. Archit. Lett., 2016

Logic-based implementation of fault-tolerant routing in 3D network-on-chips.
Proceedings of the Tenth IEEE/ACM International Symposium on Networks-on-Chip, 2016

PROSA: protocol-driven NoC architecture.
Proceedings of the Tenth IEEE/ACM International Symposium on Networks-on-Chip, 2016

Increasing the Efficiency of Latency-Driven DVFS with a Smart NoC Congestion Management Strategy.
Proceedings of the 10th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2016

Enabling HPC for QoS-sensitive applications: The MANGO approach.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

2015
Efficient and Cost-Effective Hybrid Congestion Control for HPC Interconnection Networks.
IEEE Trans. Parallel Distributed Syst., 2015

A Brief Comment on "A Complete Self-Testing and Self-Configuring NoC Infrastructure for Cost-Effective MPSoCs" [ACM Transactions on Embedded Computing Systems 12 (2013) Article 106].
ACM Trans. Embed. Comput. Syst., 2015

The fast evolving landscape of on-chip communication - Selected future challenges and research avenues.
Des. Autom. Embed. Syst., 2015

Area-efficient snoopy-aware NoC design for high-performance chip multiprocessor systems.
Comput. Electr. Eng., 2015

Customizable Heterogeneous Acceleration for Tomorrow's High-Performance Computing.
Proceedings of the 17th IEEE International Conference on High Performance Computing and Communications, 2015

On the Design of a Path-Setup Architecture for Exploiting Hybrid Photonic-Electronic NoCs.
Proceedings of the 2015 Workshop on Exploiting Silicon Photonics for Energy-Efficient High Performance Computing, 2015

Efficient DVFS Operation in NoCs Through a Proper Congestion Management Strategy.
Proceedings of the Euro-Par 2015: Parallel Processing Workshops, 2015

d<sup>2</sup>-LBDR: distance-driven routing to handle permanent failures in 2D mesh NOCs.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Synergistic use of multiple on-chip networks for ultra-low latency and scalable distributed routing reconfiguration.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

The MANGO FET-HPC Project: An Overview.
Proceedings of the 18th IEEE International Conference on Computational Science and Engineering, 2015

2014
Path-Based Partitioning Methods for 3D Networks-on-Chip with Minimal Adaptive Routing.
IEEE Trans. Computers, 2014

Efficient Routing in Heterogeneous SoC Designs with Small Implementation Overhead.
IEEE Trans. Computers, 2014

Runtime home mapping for effective memory resource usage.
Microprocess. Microsystems, 2014

Achieving balanced buffer utilization with a proper co-design of flow control and routing algorithm.
Proceedings of the Eighth IEEE/ACM International Symposium on Networks-on-Chip, 2014

ICARO: Congestion isolation in networks-on-chip.
Proceedings of the Eighth IEEE/ACM International Symposium on Networks-on-Chip, 2014

2013
An Effective and Feasible Congestion Management Technique for High-Performance MINs with Tag-Based Distributed Routing.
IEEE Trans. Parallel Distributed Syst., 2013

A complete self-testing and self-configuring NoC infrastructure for cost-effective MPSoCs.
ACM Trans. Embed. Comput. Syst., 2013

Introduction to the special section on on-chip and off-chip network architectures.
ACM Trans. Embed. Comput. Syst., 2013

Many-cores and On-chip Interconnects (NII Shonan Meeting 2013-8).
NII Shonan Meet. Rep., 2013

Silicon-aware distributed switch architecture for on-chip networks.
J. Syst. Archit., 2013

Built-in fast gather control network for efficient support of coherence protocols.
IET Comput. Digit. Tech., 2013

Adaptive routing and Dynamic Frequency Scaling for NoC power-performance optimizations.
Proceedings of the 2013 23rd International Workshop on Power and Timing Modeling, 2013

An NoC and cache hierarchy substrate to address effective virtualization and fault-tolerance.
Proceedings of the 2013 Seventh IEEE/ACM International Symposium on Networks-on-Chip (NoCS), 2013

Optimizing the overhead for network-on-chip routing reconfiguration in parallel multi-core platforms.
Proceedings of the 2013 International Symposium on System on Chip, 2013

CASS Introduction.
Proceedings of the 2013 IEEE International Symposium on Parallel & Distributed Processing, 2013

Head-of-Line Blocking Avoidance in Networks-on-Chip.
Proceedings of the 2013 IEEE International Symposium on Parallel & Distributed Processing, 2013

A fast algorithm for runtime reconfiguration to maximize the lifetime of nanoscale NoCs.
Proceedings of the 2013 Interconnection Network Architecture: On-Chip, Multi-Chip, 2013

Power Saving by NoC Traffic Compression.
Proceedings of the Euro-Par 2013: Parallel Processing Workshops, 2013

Towards Efficient Dynamic LLC Home Bank Mapping with NoC-Level Support.
Proceedings of the Euro-Par 2013 Parallel Processing, 2013

A Lightweight Network of IDs to Quickly Deliver Simple Control Messages.
Proceedings of the Euro-Par 2013: Parallel Processing Workshops, 2013

Making the Network Scalable: Inter-subnet Routing in InfiniBand.
Proceedings of the Euro-Par 2013 Parallel Processing, 2013

2012
A Survey and Evaluation of Topology-Agnostic Deterministic Routing Algorithms.
IEEE Trans. Parallel Distributed Syst., 2012

On the Impact of Within-Die Process Variation in GALS-Based NoC Performance.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

Network-on-Chip virtualization in Chip-Multiprocessor Systems.
J. Syst. Archit., 2012

Special issue on Communication Architectures for Scalable Systems.
J. Parallel Distributed Comput., 2012

OSR-Lite: Fast and deadlock-free NoC reconfiguration framework.
Proceedings of the 2012 International Conference on Embedded Computer Systems: Architectures, 2012

Exploring NoC Virtualization Alternatives in CMPs.
Proceedings of the 20th Euromicro International Conference on Parallel, 2012

Transient and Permanent Error Control for High-End Multiprocessor Systems-on-Chip.
Proceedings of the 2012 Sixth IEEE/ACM International Symposium on Networks-on-Chip (NoCS), 2012

Heterogeneous NoC Design for Efficient Broadcast-based Coherence Protocol Support.
Proceedings of the 2012 Sixth IEEE/ACM International Symposium on Networks-on-Chip (NoCS), 2012

Enabling High-Performance Crossbars through a Floorplan-Aware Design.
Proceedings of the 41st International Conference on Parallel Processing, 2012

Quest for the ultimate network-on-chip: the NaNoC project.
Proceedings of the 2012 Interconnection Network Architecture, 2012

Heterogeneous network design for effective support of invalidation-based coherency protocols.
Proceedings of the 2012 Interconnection Network Architecture, 2012

DESA: Distributed Elastic Switch Architecture for efficient networks-on-FPGAS.
Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

Dynamic Last-Level Cache Allocation to Reduce Area and Power Overhead in Directory Coherence Protocols.
Proceedings of the Euro-Par 2012 Parallel Processing - 18th International Conference, 2012

Detecting Sharing Patterns in Industrial Parallel Applications for Embedded Heterogeneous Multicore Systems.
Proceedings of the Euro-Par 2012: Parallel Processing Workshops, 2012

2011
Switch Architecture.
Proceedings of the Encyclopedia of Parallel Computing, 2011

Flow Control.
Proceedings of the Encyclopedia of Parallel Computing, 2011

Cost-Efficient On-Chip Routing Implementations for CMP and MPSoC Systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

Virtualizing network-on-chip resources in chip-multiprocessors.
Microprocess. Microsystems, 2011

A low-latency modular switch for CMP systems.
Microprocess. Microsystems, 2011

Characterizing the impact of process variation on 45 nm NoC-based CMPs.
J. Parallel Distributed Comput., 2011

OBQA: Smart and cost-efficient queue scheme for Head-of-Line blocking elimination in fat-trees.
J. Parallel Distributed Comput., 2011

A Communication-Driven Routing Technique for Application-Specific NoCs.
Int. J. Parallel Program., 2011

Cost-effective queue schemes for reducing head-of-line blocking in fat-trees.
Concurr. Comput. Pract. Exp., 2011

Fault-Tolerant Vertical Link Design for Effective 3D Stacking.
IEEE Comput. Archit. Lett., 2011

Spidergon STNoC design flow.
Proceedings of the NOCS 2011, 2011

Efficient routing implementation in complex systems-on-chip.
Proceedings of the NOCS 2011, 2011

NoC Reconfiguration for CMP Virtualization.
Proceedings of The Tenth IEEE International Symposium on Networking Computing and Applications, 2011

A Distributed Switch Architecture for On-Chip Networks.
Proceedings of the International Conference on Parallel Processing, 2011

Combining Congested-Flow Isolation and Injection Throttling in HPC Interconnection Networks.
Proceedings of the International Conference on Parallel Processing, 2011

PC-Mesh: A Dynamic Parallel Concentrated Mesh.
Proceedings of the International Conference on Parallel Processing, 2011

A power-efficient network on-chip topology.
Proceedings of the Fifth International Workshop on Interconnection Network Architecture, 2011

A fast centralized computation routing algorithm for self-configuring NoC systems.
Proceedings of the 18th International Conference on High Performance Computing, 2011

Towards an Efficient NoC Topology through Multiple Injection Ports.
Proceedings of the 14th Euromicro Conference on Digital System Design, 2011

HPC-Mesh: A Homogeneous Parallel Concentrated Mesh for Fault-Tolerance and Energy Savings.
Proceedings of the 2011 ACM/IEEE Symposium on Architectures for Networking and Communications Systems (ANCS), 2011

2010
Buffer Management Strategies to Reduce HoL Blocking.
IEEE Trans. Parallel Distributed Syst., 2010

Addressing Manufacturing Challenges with Cost-Efficient Fault Tolerant Routing.
Proceedings of the NOCS 2010, 2010

Improving the Performance of GALS-Based NoCs in the Presence of Process Variation.
Proceedings of the NOCS 2010, 2010

Welcome to CAC/SSPS 2010.
Proceedings of the 24th IEEE International Symposium on Parallel and Distributed Processing, 2010

Cost-Effective Congestion Management for Interconnection Networks Using Distributed Deterministic Routing.
Proceedings of the 16th IEEE International Conference on Parallel and Distributed Systems, 2010

VCTlite: Towards an efficient implementation of virtual cut-through switching in on-chip networks.
Proceedings of the 2010 International Conference on High Performance Computing, 2010

High Performance Networks.
Proceedings of the Euro-Par 2010 - Parallel Processing, 16th International Euro-Par Conference, Ischia, Italy, August 31, 2010

A Latency-Efficient Router Architecture for CMP Systems.
Proceedings of the 13th Euromicro Conference on Digital System Design, 2010

2009
Region-Based Routing: A Mechanism to Support Efficient Routing Algorithms in NoCs.
IEEE Trans. Very Large Scale Integr. Syst., 2009

A Switch Architecture Guaranteeing QoS Provision and HOL Blocking Elimination.
IEEE Trans. Parallel Distributed Syst., 2009

Efficient implementation of distributed routing algorithms for NoCs.
IET Comput. Digit. Tech., 2009

A performance evaluation of 2D-mesh, ring, and crossbar interconnects for chip multi-processors.
Proceedings of the Second International Workshop on Network on Chip Architectures, 2009

Flexible DOR routing for virtualization of multicore chips.
Proceedings of the 2008 IEEE International Symposium on System-on-Chip, 2009

Yield-oriented evaluation methodology of network-on-chip routing implementations.
Proceedings of the 2008 IEEE International Symposium on System-on-Chip, 2009

Dependability Analysis of a Fault-Tolerant Network Reconfiguring Strategy.
Proceedings of the Euro-Par 2009 Parallel Processing, 2009

2008
An Efficient and Deadlock-Free Network Reconfiguration Protocol.
IEEE Trans. Computers, 2008

On the Potential of NoC Virtualization for Multicore Chips.
Scalable Comput. Pract. Exp., 2008

Logic-Based Distributed Routing for NoCs.
IEEE Comput. Archit. Lett., 2008

High-radix crossbar switches enabled by proximity communication.
Proceedings of the ACM/IEEE Conference on High Performance Computing, 2008

An Efficient Implementation of Distributed Routing Algorithms for NoCs.
Proceedings of the Second International Symposium on Networks-on-Chips, 2008

Efficient unicast and multicast support for CMPs.
Proceedings of the 41st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-41 2008), 2008

Epoch-based reconfiguration: Fast, simple, and effective dynamic network reconfiguration.
Proceedings of the 22nd IEEE International Symposium on Parallel and Distributed Processing, 2008

On the Potentials of Segment-Based Routing for NoCs.
Proceedings of the 2008 International Conference on Parallel Processing, 2008

FBICM: Efficient Congestion Management for High-Performance Networks Using Distributed Deterministic Routing.
Proceedings of the High Performance Computing, 2008

Topic 13: High-Performance Networks.
Proceedings of the Euro-Par 2008, 2008

CART: Communication-Aware Routing Technique for Application-Specific NoCs.
Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008

2007
Understanding cache hierarchy interactions with a program-driven simulator.
Proceedings of the 2007 Workshop on Computer Architecture Education, 2007

Boosting Ethernet Performance by Segment-Based Routing.
Proceedings of the 15th Euromicro International Conference on Parallel, 2007

Region-Based Routing: An Efficient Routing Mechanism to Tackle Unreliable Hardware in Network on Chips.
Proceedings of the First International Symposium on Networks-on-Chips, 2007

RECN-IQ: A Cost-Effective Input-Queued Switch Architecture with Congestion Management.
Proceedings of the 2007 International Conference on Parallel Processing (ICPP 2007), 2007

Integrated QoS Provision and Congestion Management for Interconnection Networks.
Proceedings of the Euro-Par 2007, 2007

2006
A Routing Methodology for Achieving Fault Tolerance in Direct Networks.
IEEE Trans. Computers, 2006

Efficient, Scalable Congestion Management for Interconnection Networks.
IEEE Micro, 2006

Segment-based routing: an efficient fault-tolerant routing algorithm for meshes and tori.
Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), 2006

RECN-DD: A Memory-Efficient Congestion Management Technique for Advanced Switching.
Proceedings of the 2006 International Conference on Parallel Processing (ICPP 2006), 2006

Destination-Based HoL Blocking Elimination.
Proceedings of the 12th International Conference on Parallel and Distributed Systems, 2006

Reachability-Based Fault-Tolerant Routing.
Proceedings of the 12th International Conference on Parallel and Distributed Systems, 2006

Towards a Cost-Effective Interconnection Network Architecture with QoS and Congestion Management Support.
Proceedings of the Euro-Par 2006, Parallel Processing, 12th International Euro-Par Conference, Dresden, Germany, August 28, 2006

Towards an efficient switch architecture for high-radix switches.
Proceedings of the 2006 ACM/IEEE Symposium on Architecture for Networking and Communications Systems, 2006

2005
Enforcing in-order packet delivery in system area networks with adaptive routing.
J. Parallel Distributed Comput., 2005

Studying the Effect of the Design Parameters on the Interconnection Network Performance in NOWs.
Proceedings of the 13th Euromicro Workshop on Parallel, 2005

A Scalable Methodology for Computing Fault-Free Paths in InfiniBand Torus Networks.
Proceedings of the High-Performance Computing - 6th International Symposium, 2005

In-Order Packet Delivery in Interconnection Networks using Adaptive Routing.
Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 2005

Efficient Reduction of HOL Blocking in Multistage Networks.
Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 2005

A New Scalable and Cost-Effective Congestion Management Strategy for Lossless Multistage Interconnection Networks.
Proceedings of the 11th International Conference on High-Performance Computer Architecture (HPCA-11 2005), 2005

Dynamic Evolution of Congestion Trees: Analysis and Impact on Switch Architecture.
Proceedings of the High Performance Embedded Architectures and Compilers, 2005

On the Correct Sizing on Meshes Through an Effective Congestion Management Strategy.
Proceedings of the Euro-Par 2005, Parallel Processing, 11th International Euro-Par Conference, Lisbon, Portugal, August 30, 2005

Cost / Performance Trade-Offs and Fairness Evaluation of Queue Mapping Policies.
Proceedings of the Euro-Par 2005, Parallel Processing, 11th International Euro-Par Conference, Lisbon, Portugal, August 30, 2005

2004
Comparing Adaptive Routing and Dynamic Voltage Scaling for Link Power Reduction.
IEEE Comput. Archit. Lett., 2004

An Efficient Fault-Tolerant Routing Methodology for Meshes and Tori.
IEEE Comput. Archit. Lett., 2004

A Cost-Effective Technique to Reduce HOL Blocking in Single-Stage and Multistage Switch Fabrics.
Proceedings of the 12th Euromicro Workshop on Parallel, 2004

A Fully Adaptive Fault-Tolerant Routing Methodology Based on Intermediate Nodes.
Proceedings of the Network and Parallel Computing, IFIP International Conference, 2004

A Transition-Based Fault-Tolerant Routing Methodology for InfiniBand Networks.
Proceedings of the 18th International Parallel and Distributed Processing Symposium (IPDPS 2004), 2004

An Effective Fault-Tolerant Routing Methodology for Direct Networks.
Proceedings of the 33rd International Conference on Parallel Processing (ICPP 2004), 2004

LASH-TOR: A Generic Transition-Oriented Routing Algorithm.
Proceedings of the 10th International Conference on Parallel and Distributed Systems, 2004

Simple Deadlock-Free Dynamic Network Reconfiguration.
Proceedings of the High Performance Computing, 2004

A New Adaptive Fault-Tolerant Routing Methodology for Direct Networks.
Proceedings of the High Performance Computing, 2004

2003
Applying In-Transit Buffers to Boost the Performance of Networks with Source Routing.
IEEE Trans. Computers, 2003

Supporting adaptive routing in IBA switches.
J. Syst. Archit., 2003

Supporting Adaptive Routing in InfiniBand Networks.
Proceedings of the 11th Euromicro Workshop on Parallel, 2003

Performance Evaluation of COWs under Real Parallel Application.
Proceedings of the 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 2003

Supporting Fully Adaptive Routing in InfiniBand Networks.
Proceedings of the 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 2003

VOQSW: A Methodology to Reduce HOL Blocking in InfiniBand Networks.
Proceedings of the 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 2003

Routing in InfiniBandTM Torus Network Topologie.
Proceedings of the 32nd International Conference on Parallel Processing (ICPP 2003), 2003

Low-Fragmentation Mapping Strategies for Linear Forwarding Tables in InfiniBand<sup>TM</sup>.
Proceedings of the Euro-Par 2003. Parallel Processing, 2003

2002
Boosting the Performance of Myrinet Networks.
IEEE Trans. Parallel Distributed Syst., 2002

Removing the Latency Overhead of the ITB Mechanism in COWs with Source Routing.
Proceedings of the 10th Euromicro Workshop on Parallel, 2002

Improving InfiniBand Routing through Multiple Virtual Networks.
Proceedings of the High Performance Computing, 4th International Symposium, 2002

Analyzing the Influence of Virtual Lanes on the Performance of InfiniBand Networks.
Proceedings of the 16th International Parallel and Distributed Processing Symposium (IPDPS 2002), 2002

Evaluation of Alternative Arbitration Policies for Myrinet Switches.
Proceedings of the 16th International Parallel and Distributed Processing Symposium (IPDPS 2002), 2002

Effective Methodology for Deadlock-Free Minimal Routing in InfiniBand Networks.
Proceedings of the 31st International Conference on Parallel Processing (ICPP 2002), 2002

Evaluation of Routing Algorithms for InfiniBand Networks (Research Note).
Proceedings of the Euro-Par 2002, 2002

2001
Improving Network Performance by Reducing Network Contention in Source-Based COWs with a Low Path-Computation Overhead.
Proceedings of the 15th International Parallel & Distributed Processing Symposium (IPDPS-01), 2001

A First Implementation of In-Transit Buffers on Myrinet GM Software.
Proceedings of the 15th International Parallel & Distributed Processing Symposium (IPDPS-01), 2001

Deadlock-Free Routing in InfiniBand through Destination Renaming.
Proceedings of the 2001 International Conference on Parallel Processing, 2001

2000
Combining In-Transit Buffers with Optimized Routing Schemes to Boost the Performance of Networks with Source Routing.
Proceedings of the High Performance Computing, Third International Symposium, 2000

Improving Routing Performance in Myrinet Networks.
Proceedings of the 14th International Parallel & Distributed Processing Symposium (IPDPS'00), 2000

Performance evaluation of a new routing strategy for irregular networks with source routing.
Proceedings of the 14th international conference on Supercomputing, 2000

Improving the Performance of Regular Networks with Source Routing.
Proceedings of the 2000 International Conference on Parallel Processing, 2000

1999
Performance Evaluation of Networks of Workstations with Hardware Shared Memory Model Using Execution-Driven Simulation.
Proceedings of the International Conference on Parallel Processing 1999, 1999

1998
Edinet: An Execution Driven Interconnection Network Simulator for DSM Systems.
Proceedings of the Computer Performance Evaluation: Modelling Techniques and Tools, 1998


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