Roselyne Chotin

Orcid: 0000-0001-7990-9070

According to our database1, Roselyne Chotin authored at least 10 papers between 2002 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2023
Improving Integrated Circuit Security Using Mathematical Model Based on Clique Covering Reformulation.
Proceedings of the 9th International Conference on Control, 2023

2022
Model to Hardware: System-level Modeling for Wearable Devices.
Proceedings of the 10th International Conference on Model-Driven Engineering and Software Development, 2022

Using HLS for Designing a Parametric Optical Flow Hierarchical Algorithm in FPGAs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

2021
FPGA Acceleration of the Horn and Schunck Hierarchical Algorithm.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

Toward an Implementation Modeling Methodology for Designing SCA resilient Cryptographic Circuits.
Proceedings of the 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2021

2020
A HDL Generator for Flexible and Efficient Finite-Field Multipliers on FPGAs.
Proceedings of the Arithmetic of Finite Fields - 8th International Workshop, 2020

Model-Based Virtual Prototyping of CPS: Application to Bio-Medical Devices.
Proceedings of the Model-Driven Engineering and Software Development, 2020

High-level Partitioning and Design Space Exploration for Cyber Physical Systems.
Proceedings of the 8th International Conference on Model-Driven Engineering and Software Development, 2020

Virtual Prototyping of Open Source Heterogeneous Systems with an Open Source Framework Featuring SystemC MDVP Extensions.
Proceedings of the Forum for Specification and Design Languages, 2020

2002
A floating-point unit using stochastic arithmetic compliant with the IEEE-754 standard.
Proceedings of the 2002 9th IEEE International Conference on Electronics, 2002


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