Lilia Zaourar

Orcid: 0000-0002-6660-4347

According to our database1, Lilia Zaourar authored at least 25 papers between 2010 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
Design Space Exploration of HPC Systems with Random Forest-based Bayesian Optimization.
Proceedings of the 16th Workshop on Rapid Simulation and Performance Evaluation for Design, 2024

2023
A Hypergraph Model and Associated Optimization Strategies for Path Length-Driven Netlist Partitioning.
Proceedings of the Computational Science - ICCS 2023, 2023

Path Length-Driven Hypergraph Partitioning: An Integer Programming Approach.
Proceedings of the 18th Conference on Computer Science and Intelligence Systems, 2023

A-DECA: An Automated Design Space Exploration Approach for Computing Architectures to Develop Efficient High-Performance Many-Core Processors.
Proceedings of the 26th Euromicro Conference on Digital System Design, 2023

Improving Integrated Circuit Security Using Mathematical Model Based on Clique Covering Reformulation.
Proceedings of the 9th International Conference on Control, 2023

2022
Decoupling processor and memory hierarchy simulators for efficient design space exploration.
Proceedings of the DroneSE and RAPIDO '22: System Engineering for constrained embedded systems, Budapest Hungary, January 17, 2022

2021
Co-simulation of a Model Predictive Control System for Automotive Applications.
Proceedings of the Software Engineering and Formal Methods. SEFM 2021 Collocated Workshops, 2021


2020
Efficient algorithm for scheduling parallel applications on hybrid multicore machines with communications delays and energy constraint.
Concurr. Comput. Pract. Exp., 2020

Cross-level Co-simulation and Verification of an Automatic Transmission Control on Embedded Processor.
Proceedings of the Software Engineering and Formal Methods. SEFM 2020 Collocated Workshops, 2020

Polynomial Scheduling Algorithm for Parallel Applications on Hybrid Platforms.
Proceedings of the Combinatorial Optimization - 6th International Symposium, 2020

2018
Task management on fully heterogeneous micro-server system: Modeling and resolution strategies.
Concurr. Comput. Pract. Exp., 2018

Multi-start simulated annealing for partially-reconfigurable FPGA floorplanning.
Proceedings of the 2018 IEEE International Parallel and Distributed Processing Symposium Workshops, 2018

Approximation Algorithm for Scheduling Applications on Hybrid Multi-core Machines with Communications Delays.
Proceedings of the 2018 IEEE International Parallel and Distributed Processing Symposium Workshops, 2018

2017
Modeling of Applications and Hardware to Explore Task Mapping and Scheduling Strategies on a Heterogeneous Micro-Server System.
Proceedings of the 2017 IEEE International Parallel and Distributed Processing Symposium Workshops, 2017

Approximation Algorithm for Scheduling a Chain of Tasks on Heterogeneous Systems.
Proceedings of the Euro-Par 2017: Parallel Processing Workshops, 2017

2016
3DIP: An iterative partitioning tool for monolithic 3D IC.
Proceedings of the 2016 IEEE International 3D Systems Integration Conference, 2016

2015
Applying Operations Research to Design for Test Insertion Problems.
Proceedings of the Computational Intelligence in Digital and Network Designs and Applications, 2015

2013
Cache-aware static scheduling for hard real-time multicore systems based on communication affinities.
CoRR, 2013

2012
A Graph-Based Approach to Optimal Scan Chain Stitching Using RTL Design Descriptions.
VLSI Design, 2012

2011
A Global Optimization for Scan Chain Insertion at the RT-level.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011

A multi-objective optimization for memory BIST sharing using a genetic algorithm.
Proceedings of the 17th IEEE International On-Line Testing Symposium (IOLTS 2011), 2011

An Innovative Methodology for Scan Chain Insertion and Analysis at RTL.
Proceedings of the 20th IEEE Asian Test Symposium, 2011

2010
Recherche opérationnelle et optimisation pour la conception testable de circuits intégrés complexes. (-).
PhD thesis, 2010

A shared BIST optimization methodology for memory test.
Proceedings of the 15th European Test Symposium, 2010


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