Ruili Ren

According to our database, Ruili Ren authored at least 4 papers between 2024 and 2025.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2025

A 66.7dB-SNDR Pipelined-SAR ADC with On-Chip Bit-Weight Calibration Achieving ⃤SNDR<2.4dB Across PVT Variations.

Jinwei Zhang, Haolin Han, Ruili Ren, Shubin Liu, Zhangming Zhu

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2025

2024

A Power-Efficient Clock Circuit and Output Serializing Technique Integrated in a 12-bit 10-GS/s ADC.

Haolin Han, Shubin Liu, Hongzhi Liang, Yi Shen, Jianyu Guo, Ruili Ren, Zhangming Zhu

IEEE Trans. Circuits Syst. I Regul. Pap., April, 2024

A PVT-robust Gm-R-based residue amplifier with folded positive feedback technique.

Haolin Han, Jinwei Zhang, Ruili Ren, Yi Shen, Shubin Liu, Ruixue Ding

Microelectron. J., 2024

A 68.5 dB-SNDR, 12.4-fJ/conv.-step, 100-MS/s pipelined-SAR ADC with PVT-enhanced circuitry.

Haolin Han, Ruili Ren, Yi Shen, Ruixue Ding, Shubin Liu, Hongzhi Liang

Microelectron. J., 2024