Runjiang Dou

Orcid: 0000-0002-8674-1285

According to our database1, Runjiang Dou authored at least 17 papers between 2015 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
A 64 × 128 3D-Stacked SPAD Image Sensor for Low-Light Imaging.
Sensors, July, 2024

A Bio-Inspired Spiking Vision Chip Based on SPAD Imaging and Direct Spike Computing for Versatile Edge Vision.
IEEE J. Solid State Circuits, June, 2024

A Real-Time 2D/3D Perception Visual Vector Processor for 1920 × 1080 High-Resolution High-Speed Intelligent Vision Chips.
IEEE Trans. Circuits Syst. I Regul. Pap., February, 2024

DT-SCNN: dual-threshold spiking convolutional neural network with fewer operations and memory access for edge applications.
Frontiers Comput. Neurosci., 2024

2023
A 24.3 μJ/Image SNN Accelerator for DVS-Gesture With WS-LOS Dataflow and Sparse Methods.
IEEE Trans. Circuits Syst. II Express Briefs, November, 2023

Hierarchical Parallel Vision Processor for High-Speed Ship Detection.
IEEE Trans. Circuits Syst. II Express Briefs, March, 2023

A 128×128 15µm-Pitch DROIC with Pixel-Level 14-Bit ADC.
Proceedings of the IEEE International Conference on Integrated Circuits, 2023

A Lightweight Integer-STBP On-Chip Learning Method of Spiking Neural Networks For Edge Processors.
Proceedings of the IEEE International Conference on Integrated Circuits, 2023

2022
A Provisional Labels-Reduced, Real-Time Connected Component Labeling Algorithm for Edge Hardware.
IEEE Trans. Circuits Syst. II Express Briefs, 2022

ViP: A Hierarchical Parallel Vision Processor for Hybrid Vision Chip.
IEEE Trans. Circuits Syst. II Express Briefs, 2022

SiamMixer: A Lightweight and Hardware-Friendly Visual Object-Tracking Network.
Sensors, 2022

2021
A Compact High-Quality Image Demosaicking Neural Network for Edge-Computing Devices.
Sensors, 2021

A 32×32 Array Terahertz Sensor in 65-nm CMOS Technology.
Proceedings of the 2021 IEEE International Conference on Integrated Circuits, 2021

2020
A High-Speed Parallel FPGA Implementation of Harris Corner Detection.
Proceedings of the 2020 IEEE International Conference on Integrated Circuits, 2020

2018
A 25 fps 32 × 24 Digital CMOS Terahertz Image Sensor.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018

2016
A 91.2dB SNDR 66.2fJ/conv. dynamic amplifier based 24kHz ΔΣ modulator.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016

2015
A low power global shutter pixel with extended FD voltage swing range for large format high speed CMOS image sensor.
Sci. China Inf. Sci., 2015


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