Jian Liu

Orcid: 0000-0001-8057-2444

Affiliations:
  • Chinese Academy of Sciences, Institute of Semiconductors, State Key Laboratory of Superlattices and Microstructures, Beijing, China


According to our database1, Jian Liu authored at least 69 papers between 2015 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
A 3 THz CMOS Image Sensor.
IEEE J. Solid State Circuits, September, 2024

A 700nW Compact Temperature Sensor With a One-Point Trimmed Inaccuracy of +1.2/-1.0 °C for On-Chip Thermal Monitoring.
IEEE Trans. Circuits Syst. II Express Briefs, August, 2024

A 64 × 128 3D-Stacked SPAD Image Sensor for Low-Light Imaging.
Sensors, July, 2024

A Bio-Inspired Spiking Vision Chip Based on SPAD Imaging and Direct Spike Computing for Versatile Edge Vision.
IEEE J. Solid State Circuits, June, 2024

A Real-Time 2D/3D Perception Visual Vector Processor for 1920 × 1080 High-Resolution High-Speed Intelligent Vision Chips.
IEEE Trans. Circuits Syst. I Regul. Pap., February, 2024

A design method of bipolar junction transistor for high-precision remote temperature sensing.
Microelectron. J., 2024

A low power BJT-based CMOS temperature sensor using dynamic-distributing-bias circuit.
IEICE Electron. Express, 2024

Design of an integrated temperature and humidity sensor based on high dynamic range utilization rate ADC.
IEICE Electron. Express, 2024

DT-SCNN: dual-threshold spiking convolutional neural network with fewer operations and memory access for edge applications.
Frontiers Comput. Neurosci., 2024

A 32Gb/s NRZ Low-Bias DFB Driver with Frequency Boosting for High Efficiency Data Transmission.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

A 0.144 mm<sup>2</sup>12.5-16GHz PVT-Tolerant Dual-Path Offset-Charge-Pump-Based Fractional-N PLL Achieving 72.9 fSRMs Jitter, -271.5dB FoMN, and Sub-10% Jitter Variation.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2024

2023
A 24.3 μJ/Image SNN Accelerator for DVS-Gesture With WS-LOS Dataflow and Sparse Methods.
IEEE Trans. Circuits Syst. II Express Briefs, November, 2023

A 50Gb/s CMOS Optical Receiver With Si-Photonics PD for High-Speed Low-Latency Chiplet I/O.
IEEE Trans. Circuits Syst. I Regul. Pap., November, 2023

Hierarchical Parallel Vision Processor for High-Speed Ship Detection.
IEEE Trans. Circuits Syst. II Express Briefs, March, 2023

A 64-Gb/s Reference-Less PAM4 CDR with Asymmetrical Linear Phase Detector Soring 231.5-fsrms Clock Jitter and 0.21-pJ/bit Energy Efficiency in 40-nm CMOS.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

A O.4V-VDD 2.25-to-2.75GHz ULV-SS-PLL Achieving 236.6fsrms Jitter, -253.8dB Jitter-Power FoM, and -76.1dBc Reference Spur.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023

A 16.4kPixel 3.08-to-3.86THz Digital Real-Time CMOS Image Sensor with 73dB Dynamic Range.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023

An 800G Integrated Silicon-Photonic Transmitter based on 16-Channel Mach-Zehnder Modulator and Co-Designed 5.35pJ/bit CMOS Drivers.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

A 128×128 15µm-Pitch DROIC with Pixel-Level 14-Bit ADC.
Proceedings of the IEEE International Conference on Integrated Circuits, 2023

A 400-Gb/s 64-QAM Optical Receiver with Monolithically Integrated TIA and Balanced-PD in 45-nm SOI CMOS.
Proceedings of the IEEE International Conference on Integrated Circuits, 2023

A 64-Gb/s 0.33-pJ/bit PAM4 Receiver Analog Front-End with a Single-Stage Triple-Peaking CTLE Achieving 22.5-dB Boost in 40-nm CMOS Process.
Proceedings of the IEEE International Conference on Integrated Circuits, 2023

A Lightweight Integer-STBP On-Chip Learning Method of Spiking Neural Networks For Edge Processors.
Proceedings of the IEEE International Conference on Integrated Circuits, 2023

A 0.0035-mm<sup>2</sup> 0.42-pJ/bit 8-32-Gb/s Reference-Less CDR Incorporating Adaptively-Biased ChargeSharing Integrator, Alexander PFD, and 1-Tap DFE.
Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023

A 4-12.1-GHz Fractional-N Ring Sampling PLL Based on Adaptively-Biased PD-Merged DTC Achieving -37.6± 0.9-dBc Integrated Phase Noise, 261.9-fs RMS Jitter, and -240.6-dB FoM.
Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023

A Wideband Low-Noise Linear LiDAR Analog Front-End Achieving 1.6 GHz Bandwidth, $\boldsymbol{2.7}\ \mathbf{pA}/\mathbf{Hz}^{\boldsymbol{0.5}}$ Input Referred Noise, and 103 $\mathbf{dB}\mathbf{\Omega}$ Transimpedance Gain.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2023

A $\boldsymbol{4} \times \boldsymbol{112}-\mathbf{Gb}/\mathbf{s}$ PAM-4 Silicon-Photonic Transceiver Front-End for Linear-Drive Co-Packaged Optics.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2023

A 12.75-to-16-GHz Spur-Jitter-Joint-Optimization SS-PLL Achieving -94.55-dBc Reference Spur, 31.9-fs Integrated Jitter and -260.1-dB FoM.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2023

2022
A Provisional Labels-Reduced, Real-Time Connected Component Labeling Algorithm for Edge Hardware.
IEEE Trans. Circuits Syst. II Express Briefs, 2022

A Programmable and Flexible Vision Processor.
IEEE Trans. Circuits Syst. II Express Briefs, 2022

A 56-Gb/s Reconfigurable Silicon-Photonics Transmitter Using High-Swing Distributed Driver and 2-Tap In-Segment Feed-Forward Equalizer in 65-nm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022

Design of a PAM-4 VCSEL-Based Transceiver Front-End for Beyond-400G Short-Reach Optical Interconnects.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022

A 50-Gb/s PAM-4 Silicon-Photonic Transmitter Incorporating Lumped-Segment MZM, Distributed CMOS Driver, and Integrated CDR.
IEEE J. Solid State Circuits, 2022

Thermal field reconstruction based on weighted dictionary learning.
IET Circuits Devices Syst., 2022

A Low Supply Sensitivity CMOS Temperature Sensor Using Dynamic-Distributing-Bias Circuit.
Proceedings of the 2022 IEEE International Conference on Integrated Circuits, 2022

A 56Gb/s De-serializer with PAM-4 CDR for Chiplet Optical-I/O.
Proceedings of the 2022 IEEE International Conference on Integrated Circuits, 2022

Floorplanning and Power/Ground Network Design for A Programmable Vision Chip.
Proceedings of the 2022 IEEE International Conference on Integrated Circuits, 2022

A 224-Gb/s Inverter-Based TIA with Interleaved Active-Feedback and Distributed Peaking in 28-nm CMOS for Silicon Photonic Receivers.
Proceedings of the 2022 IEEE International Conference on Integrated Circuits, 2022

A 0.006-mm<sup>2</sup>6-to-20-Gb/s NRZ Bang-Bang Clock and Data Recovery Circuit With Dual-Path Loop.
Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2022

A 0.004-mm<sup>2</sup> O.7-V 31.654-μW BPSK Demodulator Incorporating Dual-Path Loop Self-Biased PLL.
Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2022

A 50-Gb/s NRZ Receiver Targeting Low-Latency Multi-Chip Module Optical I/O in 45-nm SOI CMOS.
Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2022

2021
Application of Memristors in Hardware Security: A Current State-of-the-Art Technology.
Adv. Intell. Syst., 2021

A 4×25-Gb/s Serializer with Integrated CDR and 3-Tap FFE Driver for NIC Optical Interconnects.
Proceedings of the 2021 IEEE International Conference on Integrated Circuits, 2021

A 4×25Gb/s De-Serializer with Baud-Rate Sampling CDR and Standing-Wave Clock Distribution for NIC Optical Interconnects.
Proceedings of the 2021 IEEE International Conference on Integrated Circuits, 2021

A Fast-Transient Capacitor-Less Low-Dropout Regulator for Wideband Optical Transceivers.
Proceedings of the 2021 IEEE International Conference on Integrated Circuits, 2021

A 32×32 Array Terahertz Sensor in 65-nm CMOS Technology.
Proceedings of the 2021 IEEE International Conference on Integrated Circuits, 2021

A 50Gb/s High-Efficiency Si-Photonic Transmitter With Lump-Segmented MZM and Integrated PAM4 CDR.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2021

100Gb/s PAM-4 VCSEL Driver and TIA for Short-Reach 400G-1.6T Optical Interconnects.
Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2021

2020
A Discrete-Time Audio ΔΣ Modulator Using Dynamic Amplifier With Speed Enhancement and Flicker Noise Reduction Techniques.
IEEE J. Solid State Circuits, 2020

A 50-Gb/s PAM4 Si-Photonic Transmitter With Digital-Assisted Distributed Driver and Integrated CDR in 40-nm CMOS.
IEEE J. Solid State Circuits, 2020

A 50Gb/s PAM-4 Optical Receiver with Si-Photonic PD and Linear TIA in 40nm CMOS.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

A High-Speed Parallel FPGA Implementation of Harris Corner Detection.
Proceedings of the 2020 IEEE International Conference on Integrated Circuits, 2020

A 28GBaud High-Swing Linear Mach-Zehnder Modulators Driver for PAM-4 and Coherent Optical Communications.
Proceedings of the 2020 IEEE International Conference on Integrated Circuits, 2020

A Compact On-chip Analog Memory Cell for Storing TOF Image Signal in CMOS Process.
Proceedings of the 2020 IEEE International Conference on Integrated Circuits, 2020

A Method of Estimating FD Capacitance with Large Size Photodiode in High Speed Imaging (Invited Paper).
Proceedings of the 2020 IEEE International Conference on Integrated Circuits, 2020

2019
An 18-23 GHz 57.4-fs RMS Jitter -253.5-dB FoM Sub-Harmonically Injection-Locked All-Digital PLL With Single-Ended Injection Technique and ILFD Aided Adaptive Injection Timing Alignment Technique.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

0.1-5 GHz wideband ΔΣ fractional-N frequency synthesiser for software-defined radio application.
IET Circuits Devices Syst., 2019

A 0.45-to-1.8 GHz synthesized injection-locked bang-bang phase locked loop with fine frequency tuning circuits.
Sci. China Inf. Sci., 2019

Efficient Reservoir Encoding Method for Near-Sensor Classification with Rate-Coding Based Spiking Convolutional Neural Networks.
Proceedings of the Advances in Neural Networks - ISNN 2019, 2019

A 8-b 1GS/s 2b/cycle SAR ADC in 28-nm CMOS.
Proceedings of the 2019 IEEE Asia Pacific Conference on Circuits and Systems, 2019

2018
A 0.9-2.25-GHz Sub-0.2-mW/GHz Compact Low-Voltage Low-Power Hybrid Digital PLL With Loop Bandwidth-Tracking Technique.
IEEE Trans. Very Large Scale Integr. Syst., 2018

A Heterogeneous Parallel Processor for High-Speed Vision Chip.
IEEE Trans. Circuits Syst. Video Technol., 2018

A Fast Auto-Frequency Calibration Technique for Wideband PLL with Wide Reference Frequency Range.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018

A 25 fps 32 × 24 Digital CMOS Terahertz Image Sensor.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018

2017
A 1.25-to-6.25 GHz -237.2-dB FOM wideband self-biased PLL for multi-rate serial link data transmitter.
IEICE Electron. Express, 2017

Terahertz detector for imaging in 180-nm standard CMOS process.
Sci. China Inf. Sci., 2017

A 18-to-23 GHz -253.5dB-FoM sub-harmonically injection-locked ADPLL with ILFD aided adaptive injection timing alignment technique.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017

Detection of 3.0 THz wave with a detector in 65 nm standard CMOS process.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017

2015
A low power global shutter pixel with extended FD voltage swing range for large format high speed CMOS image sensor.
Sci. China Inf. Sci., 2015

High-speed object detection based on a hierarchical parallel vision chip.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015


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