Cong Shi
Orcid: 0000-0003-0040-4411Affiliations:
- Chongqing University, School of Microelectronics and Communication Engineerin, China
- Harvard Medical School, Schepens Eye Research Institute, Massachusetts Eye and Ear, Boston, MA, USA
- Tsinghua University, Beijing, China (PhD 2014)
- Chinese Academy of Sciences, Institute of Semiconductors, Beijing, China (PhD 2014)
According to our database1,
Cong Shi
authored at least 44 papers
between 2013 and 2024.
Collaborative distances:
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Bibliography
2024
A Real-Time 2D/3D Perception Visual Vector Processor for 1920 × 1080 High-Resolution High-Speed Intelligent Vision Chips.
IEEE Trans. Circuits Syst. I Regul. Pap., February, 2024
2023
Sensors, December, 2023
A 24.3 μJ/Image SNN Accelerator for DVS-Gesture With WS-LOS Dataflow and Sparse Methods.
IEEE Trans. Circuits Syst. II Express Briefs, November, 2023
An 8-T Processing-in-Memory SRAM Cell-Based Pixel-Parallel Array Processor for Vision Chips.
IEEE Trans. Circuits Syst. I Regul. Pap., November, 2023
An Edge Neuromorphic Hardware With Fast On-Chip Error-Triggered Learning on Compressive Sensed Spikes.
IEEE Trans. Circuits Syst. II Express Briefs, July, 2023
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., May, 2023
Low-cost real-time VLSI system for high-accuracy optical flow estimation using biological motion features and random forests.
Sci. China Inf. Sci., May, 2023
A Lightweight Integer-STBP On-Chip Learning Method of Spiking Neural Networks For Edge Processors.
Proceedings of the IEEE International Conference on Integrated Circuits, 2023
MorphBungee: A 65nm 7.2mm<sup>2</sup> 27μJ/image Digital Edge Neuromorphic Chip with On-Chip 802 Frame/s Multi-Layer Spiking Neural Network Learning.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2023
Live Demonstration: Face Recognition at The Edge Using Fast On-Chip Deep Learning Neuromorphic Chip.
Proceedings of the 5th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2023
2022
A Low-Cost FPGA Implementation of Spiking Extreme Learning Machine With On-Chip Reward-Modulated STDP Learning.
IEEE Trans. Circuits Syst. II Express Briefs, 2022
TripleBrain: A Compact Neuromorphic Hardware Core With Fast On-Chip Self-Organizing and Reinforcement Spike-Timing Dependent Plasticity.
IEEE Trans. Biomed. Circuits Syst., 2022
A Lightweight Spiking GAN Model for Memristor-centric Silicon Circuit with On-chip Reinforcement Adversarial Learning.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
MorphBungee: An Edge Neuromorphic Chip for High-Accuracy On-Chip Learning of Multiple-Layer Spiking Neural Networks.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2022
2021
DeepTempo: A Hardware-Friendly Direct Feedback Alignment Multi-Layer Tempotron Learning Rule for Deep Spiking Neural Networks.
IEEE Trans. Circuits Syst. II Express Briefs, 2021
A Low-Cost High-Speed Object Tracking VLSI System Based on Unified Textural and Dynamic Compressive Features.
IEEE Trans. Circuits Syst. II Express Briefs, 2021
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021
A Cost-Efficient High-Speed VLSI Architecture for Spiking Convolutional Neural Network Inference Using Time-Step Binary Spike Maps.
Sensors, 2021
Hapke Data Augmentation for Deep Learning-Based Hyperspectral Data Analysis With Limited Samples.
IEEE Geosci. Remote. Sens. Lett., 2021
CompSNN: A lightweight spiking neural network based on spatiotemporally compressive spike features.
Neurocomputing, 2021
A Heterogeneous Spiking Neural Network for Computationally Efficient Face Recognition.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
TripleBrain: An Edge Neuromorphic Architecture for High-accuracy Single-layer Spiking Neural Network with On-chip Self-organizing and Reinforcement Learning.
Proceedings of the 2021 IEEE International Conference on Integrated Circuits, 2021
A Pixel-Parallel Array Processor without Computational Logic for Computational Image Sensors.
Proceedings of the 2021 IEEE International Conference on Integrated Circuits, 2021
Proceedings of the 3rd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2021
Optimizing Information Theory Based Bitwise Bottlenecks for Efficient Mixed-Precision Activation Quantization.
Proceedings of the Thirty-Fifth AAAI Conference on Artificial Intelligence, 2021
2020
A High-Speed Low-Cost VLSI System Capable of On-Chip Online Learning for Dynamic Vision Sensor Data Classification.
Sensors, 2020
CoRR, 2020
Proceedings of the 2020 IEEE International Conference on Integrated Circuits, 2020
Proceedings of the 37th International Conference on Machine Learning, 2020
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020
2019
Sensors, 2019
Systolic Cube: A Spatial 3D CNN Accelerator Architecture for Low Power Video Analysis.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019
Proceedings of the 13th IEEE International Conference on ASIC, 2019
Proceedings of the 13th IEEE International Conference on ASIC, 2019
2018
IEEE Trans. Circuits Syst. Video Technol., 2018
IEEE Trans. Circuits Syst. II Express Briefs, 2018
IEEE Access, 2018
2015
A low power global shutter pixel with extended FD voltage swing range for large format high speed CMOS image sensor.
Sci. China Inf. Sci., 2015
2014
A 1000 fps Vision Chip Based on a Dynamically Reconfigurable Hybrid Architecture Comprising a PE Array Processor and Self-Organizing Map Neural Network.
IEEE J. Solid State Circuits, 2014
Sci. China Inf. Sci., 2014
Sci. China Inf. Sci., 2014
A massively parallel keypoint detection and description (MP-KDD) algorithm for high-speed vision chip.
Sci. China Inf. Sci., 2014
7.3 A 1000fps vision chip based on a dynamically reconfigurable hybrid architecture comprising a PE array and self-organizing map neural network.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
2013
Proceedings of the IEEE 10th International Conference on ASIC, 2013