Sabyasachi Das

According to our database1, Sabyasachi Das authored at least 13 papers between 2001 and 2017.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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In proceedings 
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PhD thesis 
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Links

On csauthors.net:

Bibliography

2017
Pseudo-BIST: A Novel Technique for SAR-ADC Testing.
Proceedings of the VLSI Design and Test - 21st International Symposium, 2017

2008
A Novel Hybrid Parallel-Prefix Adder Architecture With Efficient Timing-Area Characteristic.
IEEE Trans. Very Large Scale Integr. Syst., 2008

Resource sharing among mutually exclusive sum-of-product blocks for area reduction.
ACM Trans. Design Autom. Electr. Syst., 2008

A Timing-Driven Approach to Synthesize Fast Barrel Shifters.
IEEE Trans. Circuits Syst. II Express Briefs, 2008

An Inversion-Based Synthesis Approach for Area and Power Efficient Arithmetic Sum-of-Products.
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

A Timing-Driven Synthesis Technique for Arithmetic Product-of-Sum Expressions.
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

A Merged Synthesis Technique for Fast Arithmetic Blocks Involving Sum-of-Products and Shifters.
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

2006
A 56-mW 23-mm<sup>2</sup> single-chip 180-nm CMOS GPS receiver with 27.2-mW 4.1-mm<sup>2</sup> radio.
IEEE J. Solid State Circuits, 2006

Consequences of Mutation, Selection, and Physico-Chemical Properties of Encoded Proteins on Synonymous Codon Usage in Adenoviruses.
Proceedings of 4th Asia-Pacific Bioinformatics Conference. 13-16 February 2006, 2006

Trends in Codon and Amino Acid Usage in Human Pathogen Tropheryma Whipplei, the only Known Actinobacteria with Reduced Genome.
Proceedings of 4th Asia-Pacific Bioinformatics Conference. 13-16 February 2006, 2006

2004
23mm<sup>2</sup> single-chip 0.18μm CMOS GPS receiver with 28mW-4.1 mm<sup>2</sup> radio and CPU/DSP/RAM/ROM.
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004

2002
An efficient and regular routing methodology for datapath designsusing net regularity extraction.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

2001
A regularity-driven fast gridless detailed router for high frequency datapath designs.
Proceedings of the 2001 International Symposium on Physical Design, 2001


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