Sanjeev Mehta

According to our database1, Sanjeev Mehta authored at least 7 papers between 2014 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2024
Automated System for Testing and Result Analysis for Payload Controller.
Proceedings of the 33rd IEEE Asian Test Symposium, 2024

2019
A Mismatch Resilient 16-Bit 20 MS/s Pipelined ADC.
Proceedings of the 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems, 2019

Large Dynamic Range Readout Integrated Circuit for Infrared Detectors.
Proceedings of the 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems, 2019

2015
An all digital delay lock loop architecture for high precision timing generator.
Proceedings of the 19th International Symposium on VLSI Design and Test, 2015

Bipolar voltage level shifter.
Proceedings of the 19th International Symposium on VLSI Design and Test, 2015

2014
Implementation of high performance Readout Integrated Circuit.
Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014

Generic and programmable Timing Generator for CCD detectors.
Proceedings of the 2014 International Conference on Advances in Computing, 2014


  Loading...