Hari Shanker Gupta

According to our database, Hari Shanker Gupta authored at least 12 papers between 2012 and 2023.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2023

A 105-525MHz Integer-N Phase-Locked Loop in Indigenous SCL 180nm CMOS.

Shivam Nigam, Mukund Murali, Hari Shanker Gupta, Saurabh Saxena

Proceedings of the 36th International Conference on VLSI Design and 2023 22nd International Conference on Embedded Systems, 2023

2019

A Mismatch Resilient 16-Bit 20 MS/s Pipelined ADC.

Satyajit Mohapatra, Hari Shanker Gupta, Nihar Ranjan Mohapatra, Sanjeev Mehta, Arup Roy Chowdhury, Nisha Pandya

Proceedings of the 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems, 2019

Large Dynamic Range Readout Integrated Circuit for Infrared Detectors.

Hari Shanker Gupta, Sanjeev Mehta, Maryam Shojaei Baghini, Arup Roy Chowdhury, A. S. Kiran Kumar, Dinesh Kumar Sharma

Proceedings of the 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems, 2019

2018

Low Power Configurable Readout Integrated Circuit for Infrared Detector.

Hari Shanker Gupta, Pranoy Datta, Maryam Shojaei Baghini, A. S. Kiran Kumar, Dinesh Kumar Sharma

Proceedings of the 31st International Conference on VLSI Design and 17th International Conference on Embedded Systems, 2018

Mismatch Resilient 3.5-Bit MDAC with MCS-CFCS.

Satyajit Mohapatra, Hari Shanker Gupta, Nihar Ranjan Mohapatra

Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

2017

A 64b/66b Line Encoding for High Speed Serializers.

Satyajit Mohapatra, Hari Shanker Gupta, Jatindeep Singh, Nihar Ranjan Mohapatra

Proceedings of the 30th International Conference on VLSI Design and 16th International Conference on Embedded Systems, 2017

2016

Novel design of a silicon photodetector and its integration in a 4×4 CMOS pixel array.

Hari Shanker Gupta, Satyajit Mohapatra, Nihar R. Mohapatra, Dinesh Kumar Sharma

Proceedings of the 17th International Symposium on Quality Electronic Design, 2016

2015

Bipolar voltage level shifter.

Hari Shanker Gupta, Shweta Kirkire, Sunil Bhati, Ravi Shankar Chaurasia, Sanjeev Mehta, Arup Roy Choudhary, Dipen Patel, Jaymin Vaghela

Proceedings of the 19th International Symposium on VLSI Design and Test, 2015

2014

Implementation of high performance Readout Integrated Circuit.

Hari Shanker Gupta, Subhananda Chakrabarti, Maryam Shojaei Baghini, Dinesh Kumar Sharma, A. S. Kiran Kumar, Sanjeev Mehta, Sandip Paul, Ravi Shankar Chaurasia, Arup Roy Chowdhury

Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014

2013

Analysis of an Interior Penalty Method for Fourth Order Problems on Polygonal Domains.

Thirupathi Gudi, Hari Shanker Gupta, Neela Nataraj

J. Sci. Comput., 2013

A fully discrete C⁰ interior penalty Galerkin approximation of the extended Fisher-Kolmogorov equation.

Thirupathi Gudi, Hari Shanker Gupta

J. Comput. Appl. Math., 2013

2012

A numerical study of variable coefficient elliptic Cauchy problem via projection method.

Hari Shanker Gupta

Int. J. Comput. Math., 2012