Santanu Kundu

According to our database, Santanu Kundu authored at least 11 papers between 2008 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2024

Unlocking the Power of Machine Learning for Faster PCB Package and Board PDN Convergence.

Manoranjan Prasad, Santanu Kundu, Lennart Renker, Rakesh Ranjan

Proceedings of the 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, 2024

MLESD: Machine Learning Assisted Faster On-Chip ESD Convergence Strategy.

Sashank Nishad, Santanu Kundu, Nicolas Richaud, S. Mallikarjun, Manoranjan Prasad, Lennart Renker

Proceedings of the 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, 2024

2023

MLTDRC: Machine Learning Driven Faster Timing Design Rule Check Convergence.

Santanu Kundu, Chetan Suryakant Padharia, Ravi Sankar Kerla

Proceedings of the 36th International Conference on VLSI Design and 2023 22nd International Conference on Embedded Systems, 2023

2022

MLIR: Machine Learning based IR Drop Prediction on ECO Revised Design for Faster Convergence.

Santanu Kundu, Manoranjan Prasad, Sashank Nishad, Sandeep Nachireddy, Harikrishnan K

Proceedings of the 35th International Conference on VLSI Design and 2022 21st International Conference on Embedded Systems, 2022

2016

Leakage Power Minimization in Deep Sub-Micron Technology by Exploiting Positive Slacks of Dependent Paths.

Tuhin Subhra Chakraborty, Santanu Kundu, Deepak Agrawal, Sanjay Tanaji Shinde, Jacob Mathews, Rekha K. James

Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016

2012

Design and evaluation of Mesh-of-Tree based Network-on-Chip using virtual channel router.

Santanu Kundu, Soumya J., Santanu Chattopadhyay

Microprocess. Microsystems, 2012

2011

Design and Evaluation of Mesh-of-Tree Based Network-on-Chip for Two- and Three-Dimensional Integrated Circuits.

Santanu Kundu, Santanu Chattopadhyay

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011

2009

A Comparative Performance Evaluation of Network-on-Chip Architectures under Self-Similar Traffic.

Santanu Kundu, Kanchan Manna, Shobhit Gupta, Kundan Kumar, Ritesh Parikh, Santanu Chattopadhyay

Proceedings of the ARTCom 2009, 2009

2008

Network-on-chip architecture design based on mesh-of-tree deterministic routing topology.

Santanu Kundu, Santanu Chattopadhyay

Int. J. High Perform. Syst. Archit., 2008

Mesh-of-Tree Based Scalable Network-on-Chip Architecture.

Santanu Kundu, Radha Purnima Dasari, Santanu Chattopadhyay, Kanchan Manna

Proceedings of the IEEE Reglon 10 Colloquium and Third International Conference on Industrial and Information Systems, 2008

Mesh-of-tree deterministic routing for network-on-chip architecture.

Santanu Kundu, Santanu Chattopadhyay

Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008