Saurabh Chaubey

According to our database, Saurabh Chaubey authored at least 7 papers between 2014 and 2019.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of five.

2019

Design Techniques for Zero Steady-State Output Ripple in Digital Low Dropout Regulators.

Saurabh Chaubey, Meghna Madhusudan, Ramesh Harjani

Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019

A Multi-Mode DC-DC Converter for Direct Battery-to-Silicon High Tension Power Delivery in 65nm CMOS.

Saurabh Chaubey, Ramesh Harjani

Proceedings of the IEEE Custom Integrated Circuits Conference, 2019

2018

A 100MS/s 9-bit Companding SAR ADC with On-Chip Input Driver in 65nm CMOS for Multi-Carrier Communications.

Anindya Saha, Saurabh Chaubey, Ramesh Harjani

Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018

2017

Fully tunable software defined DC-DC converter with 3000X output current & 4X output voltage ranges.

Saurabh Chaubey, Ramesh Harjani

Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017

A smart-offset analog LDO with 0.3V minimum input voltage and 99.1% current efficiency.

Saurabh Chaubey, Ramesh Harjani

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017

2014

High power-density, hybrid inductive/capacitive converter with area reuse for multi-domain DVS.

Sudhir S. Kudva, Saurabh Chaubey, Ramesh Harjani

Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

A unified framework for capacitive series-parallel DC-DC converter design.

Ramesh Harjani, Saurabh Chaubey

Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014