Sudhir S. Kudva

According to our database, Sudhir S. Kudva authored at least 16 papers between 2004 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

16.4 High-Density and Low-Power PUF Designs in 5nm Achieving 23× and 39× BER Reduction After Unstable Bit Detection and Masking.

Sudhir S. Kudva, Mahmut Ersin Sinangil, Stephen G. Tell, Nikola Nedovic, Sanquan Song, Brian Zimmer, C. Thomas Gray

Proceedings of the IEEE International Solid-State Circuits Conference, 2024

2022

An FLL-Based Clock Glitch Detector for Security Circuits in a 5nm FINFET Process.

Sanquan Song, Stephen G. Tell, Brian Zimmer, Sudhir S. Kudva, Nikola Nedovic, C. Thomas Gray

Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

2020

6.6 Reference-Noise Compensation Scheme for Single-Ended Package-to-Package Links.

Xi Chen, Nikola Nedovic, Stephen G. Tell, Sudhir S. Kudva, Brian Zimmer, Thomas H. Greer, John W. Poulton, Sanquan Song, Walker J. Turner, John M. Wilson, C. Thomas Gray

Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

2019

A 1.17-pJ/b, 25-Gb/s/pin Ground-Referenced Single-Ended Serial Link for Off- and On-Package Communication Using a Process- and Temperature-Adaptive Voltage Regulator.

John W. Poulton, John M. Wilson, Walker J. Turner, Brian Zimmer, Xi Chen, Sudhir S. Kudva, Sanquan Song, Stephen G. Tell, Nikola Nedovic, Wenxu Zhao, Sunil R. Sudhakaran, C. Thomas Gray, William J. Dally

IEEE J. Solid State Circuits, 2019

A 2-to-20 GHz Multi-Phase Clock Generator with Phase Interpolators Using Injection-Locked Oscillation Buffers for High-Speed IOs in 16nm FinFET.

Sanquan Song, John Poulton, Xi Chen, Brian Zimmer, Stephen G. Tell, Walker J. Turner, Sudhir S. Kudva, Nikola Nedovic, John M. Wilson, C. Thomas Gray, William J. Dally

Proceedings of the IEEE Custom Integrated Circuits Conference, 2019

2018

A 1.17pJ/b 25Gb/s/pin ground-referenced single-ended serial link for off- and on-package communication in 16nm CMOS using a process- and temperature-adaptive voltage regulator.

John M. Wilson, Walker J. Turner, John W. Poulton, Brian Zimmer, Xi Chen, Sudhir S. Kudva, Sanquan Song, Stephen G. Tell, Nikola Nedovic, Wenxu Zhao, Sunil R. Sudhakaran, C. Thomas Gray, William J. Dally

Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

Ground-referenced signaling for intra-chip and short-reach chip-to-chip interconnects.

Walker J. Turner, John W. Poulton, John M. Wilson, Xi Chen, Stephen G. Tell, Matthew Fojtik, Thomas H. Greer, Brian Zimmer, Sanquan Song, Nikola Nedovic, Sudhir S. Kudva, Sunil R. Sudhakaran, Rizwan Bashirullah, Wenxu Zhao, William J. Dally, C. Thomas Gray

Proceedings of the 2018 IEEE Custom Integrated Circuits Conference, 2018

A switching linear regulator based on a fast-self-clocked comparator with very low probability of meta-stability and a parallel analog ripple control module.

Sudhir S. Kudva, Sanquan Song, John W. Poulton, John M. Wilson, Wenxu Zhao, C. Thomas Gray

Proceedings of the 2018 IEEE Custom Integrated Circuits Conference, 2018

2016

Modeling and Analysis of Power Supply Noise Tolerance with Fine-Grained GALS Adaptive Clocks.

Divya Akella Kamakshi, Matthew Fojtik, Brucek Khailany, Sudhir S. Kudva, Yaping Zhou, Benton H. Calhoun

Proceedings of the 22nd IEEE International Symposium on Asynchronous Circuits and Systems, 2016

2014

High power-density, hybrid inductive/capacitive converter with area reuse for multi-domain DVS.

Sudhir S. Kudva, Saurabh Chaubey, Ramesh Harjani

Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

2013

Fully Integrated Capacitive DC-DC Converter With All-Digital Ripple Mitigation Technique.

Sudhir S. Kudva, Ramesh Harjani

IEEE J. Solid State Circuits, 2013

2012

Fully integrated capacitive converter with all digital ripple mitigation.

Sudhir S. Kudva, Ramesh Harjani

Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012

2011

Fully-Integrated On-Chip DC-DC Converter With a 450X Output Range.

Sudhir S. Kudva, Ramesh Harjani

IEEE J. Solid State Circuits, 2011

2008

Quadrature generation techniques for frequency multiplication based oscillators.

Jagdish Nayayan Pandey, Bharadwaj Amrutur, Sudhir S. Kudva

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

2007

A Low Power Frequency Multiplication Technique for ZigBee Transciever.

Jagdish Nayayan Pandey, Sudhir S. Kudva, Bharadwaj Amrutur

Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

2004

Quality and complexity comparison of H.264 intra mode with JPEG2000 and JPEG.

Aravind Al, Bindu P. Rao, Sudhir S. Kudva, Sreenu Babu, David S. Sumam, Ajit V. Rao

Proceedings of the 2004 International Conference on Image Processing, 2004