Meghna Madhusudan

According to our database, Meghna Madhusudan authored at least 26 papers between 2019 and 2023.

Collaborative distances:

• Dijkstra number of three.
• Erdős number of four.

2023

A Generalized Methodology for Well Island Generation and Well-tap Insertion in Analog/Mixed-signal Layouts.

Ramprasath Srinivasa Gopalakrishnan, Meghna Madhusudan, Arvind K. Sharma, Jitesh Poojary, Soner Yaldiz, Ramesh Harjani, Steven M. Burns, Sachin S. Sapatnekar

ACM Trans. Design Autom. Electr. Syst., September, 2023

GNN-Based Hierarchical Annotation for Analog Circuits.

Kishor Kunal, Tonmoy Dhar, Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Wenbin Xu, Steven M. Burns, Jiang Hu, Ramesh Harjani, Sachin S. Sapatnekar

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., September, 2023

Constructive Placement and Routing for Common-Centroid Capacitor Arrays in Binary-Weighted and Split DACs.

Nibedita Karmokar, Arvind K. Sharma, Jitesh Poojary, Meghna Madhusudan, Ramesh Harjani, Sachin S. Sapatnekar

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., September, 2023

Performance-driven Wire Sizing for Analog Integrated Circuits.

Yaguang Li, Yishuang Lin, Meghna Madhusudan, Arvind K. Sharma, Sachin S. Sapatnekar, Ramesh Harjani, Jiang Hu

ACM Trans. Design Autom. Electr. Syst., March, 2023

MMM: Machine Learning-Based Macro-Modeling for Linear Analog ICs and ADC/DACs.

Yishuang Lin, Yaguang Li, Meghna Madhusudan, Sachin S. Sapatnekar, Ramesh Harjani, Jiang Hu

Proceedings of the 5th ACM/IEEE Workshop on Machine Learning for CAD, 2023

Understanding Distance-Dependent Variations for Analog Circuits in a FinFET Technology.

Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Ramprasath S, Kishor Kunal, Sachin S. Sapatnekar, Ramesh Harjani

Proceedings of the 53rd IEEE European Solid-State Device Research Conference, 2023

2022

Analog/Mixed-Signal Layout Optimization using Optimal Well Taps.

Ramprasath S, Meghna Madhusudan, Arvind K. Sharma, Jitesh Poojary, Soner Yaldiz, Ramesh Harjani, Steven M. Burns, Sachin S. Sapatnekar

Proceedings of the ISPD 2022: International Symposium on Physical Design, Virtual Event, Canada, March 27, 2022

Are Analytical Techniques Worthwhile for Analog IC Placement?

Yishuang Lin, Yaguang Li, Donghao Fang, Meghna Madhusudan, Sachin S. Sapatnekar, Ramesh Harjani, Jiang Hu

Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

Constructive Common-Centroid Placement and Routing for Binary-Weighted Capacitor Arrays.

Nibedita Karmokar, Arvind K. Sharma, Jitesh Poojary, Meghna Madhusudan, Ramesh Harjani, Sachin S. Sapatnekar

Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

Common-Centroid Layout for Active and Passive Devices: A Review and the Road Ahead.

Nibedita Karmokar, Meghna Madhusudan, Arvind K. Sharma, Ramesh Harjani, Mark Po-Hung Lin, Sachin S. Sapatnekar

Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022

2021

ALIGN: A System for Automating Analog Layout.

Tonmoy Dhar, Kishor Kunal, Yaguang Li, Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Wenbin Xu, Steven M. Burns, Ramesh Harjani, Jiang Hu, Desmond A. Kirkpatrick, Parijat Mukherjee, Soner Yaldiz, Sachin S. Sapatnekar

IEEE Des. Test, 2021

A Circuit Attention Network-Based Actor-Critic Learning Approach to Robust Analog Transistor Sizing.

Yaguang Li, Yishuang Lin, Meghna Madhusudan, Arvind K. Sharma, Sachin S. Sapatnekar, Ramesh Harjani, Jiang Hu

Proceedings of the 3rd ACM/IEEE Workshop on Machine Learning for CAD, 2021

Machine Learning Techniques in Analog Layout Automation.

Tonmoy Dhar, Kishor Kunal, Yaguang Li, Yishuang Lin, Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Steven M. Burns, Ramesh Harjani, Jiang Hu, Parijat Mukherjee, Soner Yaldiz, Sachin S. Sapatnekar

Proceedings of the ISPD '21: International Symposium on Physical Design, 2021

Performance-Aware Common-Centroid Placement and Routing of Transistor Arrays in Analog Circuits.

Arvind K. Sharma, Meghna Madhusudan, Steven M. Burns, Soner Yaldiz, Parijat Mukherjee, Ramesh Harjani, Sachin S. Sapatnekar

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

From Specification to Silicon: Towards Analog/Mixed-Signal Design Automation using Surrogate NN Models with Transfer Learning.

Juzheng Liu, Shiyu Su, Meghna Madhusudan, Mohsen Hassanpourghadi, Samuel Saunders, Qiaochu Zhang, Rezwan A. Rasul, Yaguang Li, Jiang Hu, Arvind Kumar Sharma, Sachin S. Sapatnekar, Ramesh Harjani, Anthony Levi, Sandeep Gupta, Mike Shuo-Wei Chen

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

Common-Centroid Layouts for Analog Circuits: Advantages and Limitations.

Arvind K. Sharma, Meghna Madhusudan, Steven M. Burns, Parijat Mukherjee, Soner Yaldiz, Ramesh Harjani, Sachin S. Sapatnekar

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

Analog Layout Generation using Optimized Primitives.

Meghna Madhusudan, Arvind K. Sharma, Yaguang Li, Jiang Hu, Sachin S. Sapatnekar, Ramesh Hajiani

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

Fast and Efficient Constraint Evaluation of Analog Layout Using Machine Learning Models.

Tonmoy Dhar, Jitesh Poojary, Yaguang Li, Kishor Kunal, Meghna Madhusudan, Arvind K. Sharma, Susmita Dey Manasi, Jiang Hu, Ramesh Harjani, Sachin S. Sapatnekar

Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021

2020

Exploring a Machine Learning Approach to Performance Driven Analog IC Placement.

Yaguang Li, Yishuang Lin, Meghna Madhusudan, Arvind K. Sharma, Wenbin Xu, Sachin S. Sapatnekar, Ramesh Harjani, Jiang Hu

Proceedings of the 2020 IEEE Computer Society Annual Symposium on VLSI, 2020

Learning from Experience: Applying ML to Analog Circuit Design.

Kishor Kunal, Tonmoy Dhar, Yaguang Li, Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Wenbin Xu, Steven M. Burns, Ramesh Harjani, Jiang Hu, Parijat Mukherjee, Sachin S. Sapatnekar

Proceedings of the ISPD 2020: International Symposium on Physical Design, Taipei, Taiwan, March 29, 2020

A Customized Graph Neural Network Model for Guiding Analog IC Placement.

Yaguang Li, Yishuang Lin, Meghna Madhusudan, Arvind K. Sharma, Wenbin Xu, Sachin S. Sapatnekar, Ramesh Harjani, Jiang Hu

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

A general approach for identifying hierarchical symmetry constraints for analog circuit layout.

Kishor Kunal, Jitesh Poojary, Tonmoy Dhar, Meghna Madhusudan, Ramesh Harjani, Sachin S. Sapatnekar

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

The ALIGN Open-Source Analog Layout Generator: v1.0 and Beyond (Invited talk).

Tonmoy Dhar, Kishor Kunal, Yaguang Li, Yishuang Lin, Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Steven M. Burns, Ramesh Harjani, Jiang Hu, Parijat Mukherjee, Soner Yaldiz, Sachin S. Sapatnekar

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

GANA: Graph Convolutional Network Based Automated Netlist Annotation for Analog Circuits.

Kishor Kunal, Tonmoy Dhar, Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Wenbin Xu, Steven M. Burns, Jiang Hu, Ramesh Harjani, Sachin S. Sapatnekar

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019

Design Techniques for Zero Steady-State Output Ripple in Digital Low Dropout Regulators.

Saurabh Chaubey, Meghna Madhusudan, Ramesh Harjani

Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019

ALIGN: Open-Source Analog Layout Automation from the Ground Up.

Kishor Kunal, Meghna Madhusudan, Arvind K. Sharma, Wenbin Xu, Steven M. Burns, Ramesh Harjani, Jiang Hu, Desmond A. Kirkpatrick, Sachin S. Sapatnekar

Proceedings of the 56th Annual Design Automation Conference 2019, 2019