Sergio D'Angelo

According to our database1, Sergio D'Angelo authored at least 21 papers between 1988 and 2013.

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Bibliography

2013
A Preliminary Study about SEU Effects on Programmable Interconnections of SRAM-based FPGAs.
J. Electron. Test., 2013

2007
Evaluation of Single Event Upset Mitigation Schemes for SRAM Based FPGAs Using the FLIPPER Fault Injection Platform.
Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007

2005
Heavy Ion Effects on Configuration Logic of Virtex FPGAs.
Proceedings of the 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 2005

2003
A Fault Injection Tool for SRAM-based FPGAs.
Proceedings of the 9th IEEE International On-Line Testing Symposium (IOLTS 2003), 2003

Radiation test methodology for SRAM-based FPGAs by using THESIC.
Proceedings of the 9th IEEE International On-Line Testing Symposium (IOLTS 2003), 2003

A Tool for Injecting SEU-Like Faults into the Configuration Control Mechanism of Xilinx Virtex FPGAs.
Proceedings of the 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 2003

2002
A Fault-Tolerant FPGA-based Multi-Stage Interconnection Network for Space Applications.
Proceedings of the 1st IEEE International Workshop on Electronic Design, 2002

2001
Novel Fault-Tolerant Adder Design for FPGA-Based Systems.
Proceedings of the 7th IEEE International On-Line Testing Workshop (IOLTW 2001), 2001

A Fault-Tolerance Scheme for a MIN-Based Multi-Sensor System.
Proceedings of the 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, 2001

A Fault-Tolerance Strategy for an FPGA-Based Multi-stage Interconnection Network in a Multi-sensor System for Space Application.
Proceedings of the 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2001), 2001

2000
EVIDENCE: An FPGA-Based System for Photon EVent IDENtification and CEntroiding.
Proceedings of the 8th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2000), 2000

Achieving Fault-Tolerance by Shifted and Rotated Operands in TMR Non-Diverse ALUs.
Proceedings of the 15th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2000), 2000

1999
Transient and Permanent Fault Diagnosis for FPGA-Based TMR Systems.
Proceedings of the 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '99), 1999

Implementing a Self-Checking Neural System for Photon Event Identification by SRAM-Based FPGAs.
Proceedings of the 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '99), 1999

1998
Experimenting Genetic Algorithms for Training a Neural Network Prototype for Photon Event Identification.
Proceedings of the Thirty-First Annual Hawaii International Conference on System Sciences, 1998

Fault-Tolerant Voting Mechanism and Recovery Scheme for TMR FPGA-Based Systems.
Proceedings of the 13th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '98), 1998

1997
Modular Design of Communication Node Prototypes.
Proceedings of the 7th Great Lakes Symposium on VLSI (GLS-VLSI '97), 1997

1995
A dedicated digital unit for event recognition and centroiding in photon counting intensified CCDs.
Proceedings of the 7th Euromicro Workshop on Real-Time Systems, 1995

1990
Computing models in designing.
Microprocessing and Microprogramming, 1990

1989
Definition of elementary arithmetic operations by using ACM.
Proceedings of the 22nd Annual Workshop and Symposium on Microprogramming and Microarchitecture, 1989

1988
Microprogramming in multiprocessor data acquisition system.
Proceedings of the 21st Annual Workshop and Symposium on Microprogramming and Microarchitecture, 1988, San Diego, California, USA, November 28, 1988


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