Valentino Liberali

Orcid: 0000-0003-1333-6876

According to our database1, Valentino Liberali authored at least 61 papers between 1993 and 2024.

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Bibliography

2024

2023
Modelling and Verification of MOS Transistors at Cryogenic Temperature.
Proceedings of the 12th International Conference on Modern Circuits and Systems Technologies, 2023


2022
The AM08 Associative Memory ASIC Design, Architecture and Evaluation methodology.
Proceedings of the 11th International Conference on Modern Circuits and Systems Technologies, 2022

2019
Design of a Charge Sensitive Amplifier for Silicon Particle Detector in BCD 180 nm Process.
Proceedings of the 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems, 2019

Design of HV-CMOS Detectors in BCD Technology with Noise and Crosstalk Measurements.
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019

2018
Enhancing logic synthesis of switching lattices by generalized Shannon decomposition methods.
Microprocess. Microsystems, 2018

A very compact population count circuit for associative memories.
Proceedings of the 7th International Conference on Modern Circuits and Systems Technologies, 2018

Characterization of an LVDS Link in 28 nm CMOS for Multi-Purpose Pattern Recognition.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

A Digitally-Controlled Ring Oscillator in 28 nm CMOS technology.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Design and Characterization of New Content Addressable Memory Cells.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018


2017
Design of LVDS driver and receiver in 28 nm CMOS technology for Associative Memories.
Proceedings of the 6th International Conference on Modern Circuits and Systems Technologies, 2017

Heterogeneous computing system platform for high-performance pattern recognition applications.
Proceedings of the 6th International Conference on Modern Circuits and Systems Technologies, 2017

Power Distribution Network optimization for Associative Memories.
Proceedings of the 6th International Conference on Modern Circuits and Systems Technologies, 2017

Population count circuits for Associative Memories: A comparison study.
Proceedings of the 6th International Conference on Modern Circuits and Systems Technologies, 2017

A low-power and high-density Associative Memory in 28 nm CMOS technology.
Proceedings of the 6th International Conference on Modern Circuits and Systems Technologies, 2017

2016
Logic Synthesis for Switching Lattices by Decomposition with P-Circuits.
Proceedings of the 2016 Euromicro Conference on Digital System Design, 2016

2015

A subthreshold, low-power, RHBD reference circuit, for earth observation and communication satellites.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Double-redundant design methodology to improve radiation hardness in pixel detector readout ICs.
Proceedings of the 2015 IEEE International Conference on Electronics, 2015


Role of IC substrate and ESD protections in noise propagation: Design and modelling of dedicated test chip in 40 nm technology.
Proceedings of the 10th International Workshop on the Electromagnetic Compatibility of Integrated Circuits, 2015

2014
The start-up circuit for a low voltage bandgap reference.
Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014

Radiation-tolerant standard cell synthesis using double-rail redundant approach.
Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014

Characterisation of an Associative Memory Chip for high-energy physics experiments.
Proceedings of the IEEE International Instrumentation and Measurement Technology Conference, 2014

2013
A Preliminary Study about SEU Effects on Programmable Interconnections of SRAM-based FPGAs.
J. Electron. Test., 2013

Design methodology for low-power embedded microprocessors.
Proceedings of the 2013 23rd International Workshop on Power and Timing Modeling, 2013

Evaluating the impact of substrate on power integrity in industrial microcontrollers.
Proceedings of the 2013 23rd International Workshop on Power and Timing Modeling, 2013

Exploiting body biasing for leakage reduction: A case study.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2013

Evaluating the impact of substrate noise on conducted EMI in automotive microcontrollers.
Proceedings of the 9th International Workshop on Electromagnetic Compatibility of Integrated Circuits, 2013

2012
Synthesis of P-circuits for logic restructuring.
Integr., 2012

A new XOR-based Content Addressable Memory architecture.
Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

2011
An approximation algorithm for cofactoring-based synthesis.
Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011

2010
Properties of Digital Switching Currents in Fully CMOS Combinational Logic.
IEEE Trans. Very Large Scale Integr. Syst., 2010

Analysis and Measurement of Crosstalk Effects on Mixed-Signal CMOS ICs With Different Mounting Technologies.
IEEE Trans. Instrum. Meas., 2010

2009
A radiation hardened 512 kbit SRAM in 180 nm CMOS technology.
Proceedings of the 16th IEEE International Conference on Electronics, 2009

2008
A Comparison between Two Logic Synthesis Forms from Digital Switching Noise Viewpoint.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2008

Design of a rad-hard library of digital cells for space applications.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

2007
Effects of digital switching noise on analog circuits performance.
Proceedings of the 18th European Conference on Circuit Theory and Design, 2007

2006
Effects of digital switching noise on analog voltage references in mixed-signal CMOS ICs.
Proceedings of the 19th Annual Symposium on Integrated Circuits and Systems Design, 2006

2004
An approach to computer simulation of bonding and package crosstalk in mixed-signal CMOS ICs.
Proceedings of the 17th Annual Symposium on Integrated Circuits and Systems Design, 2004

A Study of Crosstalk Through Bonding and Package Parasitics in CMOS Mixed Analog-Digital Circuits.
Proceedings of the Integrated Circuit and System Design, 2004

2003
A digital self-calibration circuit for absolute optical rotary encoder microsystems.
IEEE Trans. Instrum. Meas., 2003

Model and verification of triple-well shielding on substrate noise in mixed-signal CMOS ICs.
Proceedings of the ESSCIRC 2003, 2003

2002
A multiplierless decimation filter for ΣΔ A/D conversion.
Proceedings of the 2002 9th IEEE International Conference on Electronics, 2002

2001
An automatically compensated readout channel for rotary encoder systems.
IEEE Trans. Instrum. Meas., 2001

Design solutions for low-power digital filters.
Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001

Generation of Optimal Unit Distance Codes for Rotary Encoders through Simulated Evolution.
Proceedings of the Applications of Evolutionary Computing, 2001

An Evolutionary Approach to Automatic Generation of VHDL Code for Low-Power Digital Filters.
Proceedings of the Genetic Programming, 4th European Conference, 2001

2000
Dynamic Optimisation of Non-linear Feed Forward Circuits.
Proceedings of the Evolvable Systems: From Biology to Hardware, 2000

CMOS front-end for optical rotary encoders.
Proceedings of the 2000 7th IEEE International Conference on Electronics, 2000

1999
On-Line Evolution of FPGA-Based Circuits: A Case Study on Hash Functions.
Proceedings of the 1st NASA / DoD Workshop on Evolvable Hardware (EH '99), 1999

1998
Signal Processing for Smart Sensors.
Proceedings of the 11th Annual Symposium on Integrated Circuits Design, 1998

Automatic Synthesis of Hashing Function Circuits using Evolutionary Techniques.
Proceedings of the 11th Annual Symposium on Integrated Circuits Design, 1998

Evolutionary Design of Hashing Function Circuits Using an FPGA.
Proceedings of the Evolvable Systems: From Biology to Hardware, 1998

Efficient implementation of multiplier-free decimation filters for ΣΔ A/D conversion.
Proceedings of the 5th IEEE International Conference on Electronics, Circuits and Systems, 1998

1996
Design of high-performance band-pass sigma-delta modulator with concurrent error detection.
Proceedings of Third International Conference on Electronics, Circuits, and Systems, 1996

1993
TOSCA: a simulator for switched-capacitor noise-shaping A/D converters.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993

Automatic Generation of Transistor Stacks for CMOS Analog Layout.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993

Multiplier-free Lagrange interpolators for oversampled D/A converters.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993


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