Seunghwan Lee
Orcid: 0000-0003-3137-9335Affiliations:
- Pohang University of Science and Technology (POSTECH), Department of Electrical Engineering, Korea
According to our database1,
Seunghwan Lee
authored at least 11 papers
between 2019 and 2025.
Collaborative distances:
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Bibliography
2025
Patterned Multi-Wall Nanosheet FETs for Sustainable Scaling: Zero Gate Extension With Minimal Gate Cut Width.
IEEE Access, 2025
2024
Nonlinear Variation Decomposition of Neural Networks for Holistic Semiconductor Process Monitoring.
Adv. Intell. Syst., October, 2024
Neural Compact Modeling Framework for Flexible Model Parameter Selection with High Accuracy and Fast SPICE Simulation.
Adv. Intell. Syst., April, 2024
Multi-Task Learning for Real-Time BSIM-CMG Parameter Extraction of NSFETs With Multiple Structural Variations.
IEEE Access, 2024
2022
DC Performance Variations by Grain Boundary in Source/Drain Epitaxy of Sub-3-nm Nanosheet Field-Effect Transistors.
IEEE Access, 2022
2021
Digital/Analog Performance Optimization of Vertical Nanowire FETs Using Machine Learning.
IEEE Access, 2021
Monolithic 3D 6T-SRAM Based on Newly Designed Gate and Source/Drain Bottom Contact Schemes.
IEEE Access, 2021
2020
Comprehensive Analysis of Source and Drain Recess Depth Variations on Silicon Nanosheet FETs for Sub 5-nm Node SoC Application.
IEEE Access, 2020
2019
Source/Drain Patterning FinFETs as Solution for Physical Area Scaling Toward 5-nm Node.
IEEE Access, 2019
Bottom Oxide Bulk FinFETs Without Punch-Through-Stopper for Extending Toward 5-nm Node.
IEEE Access, 2019
Punch-Through-Stopper Free Nanosheet FETs With Crescent Inner-Spacer and Isolated Source/Drain.
IEEE Access, 2019