Seungjin Lee
Orcid: 0000-0002-1130-7767Affiliations:
- Korea Advanced Institute of Science and Technology (KAIST), Department of Electrical Engineering, Daejeon, Korea
According to our database1,
Seungjin Lee
authored at least 47 papers
between 2006 and 2023.
Collaborative distances:
Collaborative distances:
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Bibliography
2023
An Energy-Efficient Multi-Level Sleep Strategy for Periodic Uplink Transmission in Industrial Private 5G Networks.
Sensors, November, 2023
Energy-Efficient AP Selection Using Intelligent Access Point System to Increase the Lifespan of IoT Devices.
Sensors, 2023
2022
A Novel Energy-Conscious Access Point (eAP) System With Cross-Layer Design in Wi-Fi Networks for Reliable IoT Services.
IEEE Access, 2022
2013
1.2-mW Online Learning Mixed-Mode Intelligent Inference Engine for Low-Power Real-Time Object Recognition Processor.
IEEE Trans. Very Large Scale Integr. Syst., 2013
A 320 mW 342 GOPS Real-Time Dynamic Object Recognition Processor for HD 720p Video Streams.
IEEE J. Solid State Circuits, 2013
An 86 mW 98GOPS ANN-Searching Processor for Full-HD 30 fps Video Object Recognition With Zeroless Locality-Sensitive Hashing.
IEEE J. Solid State Circuits, 2013
2012
IEEE Micro, 2012
A 92-mW Real-Time Traffic Sign Recognition System With Robust Illumination Adaptation and Support Vector Machine.
IEEE J. Solid State Circuits, 2012
A 320mW 342GOPS real-time moving object recognition processor for HD 720p video streams.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
A simultaneous multithreading heterogeneous object recognition processor with machine learning based dynamic resource management.
Proceedings of the 2012 IEEE Symposium on Low-Power and High-Speed Chips, 2012
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012
2011
24-GOPS 4.5-mm<sup>2</sup> Digital Cellular Neural Network for Rapid Visual Attention in an Object-Recognition SoC.
IEEE Trans. Neural Networks, 2011
Photonic Netw. Commun., 2011
A 345 mW Heterogeneous Many-Core Processor With an Intelligent Inference Engine for Robust Object Recognition.
IEEE J. Solid State Circuits, 2011
A 57mW embedded mixed-mode neuro-fuzzy accelerator for intelligent multi-core processor.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
A 92mW real-time traffic sign recognition system with robust light and dark adaptation.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011
2010
Visual Image Processing RAM: Memory Architecture With 2-D Data Location Search and Data Consistency Management for a Multicore Object Recognition Processor.
IEEE Trans. Circuits Syst. Video Technol., 2010
An attention controlled multi-core architecture for energy efficient object recognition.
Signal Process. Image Commun., 2010
Familiarity based unified visual attention model for fast and robust object recognition.
Pattern Recognit., 2010
A 118.4 GB/s Multi-Casting Network-on-Chip With Hierarchical Star-Ring Combined Topology for Real-Time Object Recognition.
IEEE J. Solid State Circuits, 2010
A 201.4 GOPS 496 mW Real-Time Multi-Object Recognition Processor With Bio-Inspired Neural Perception Engine.
IEEE J. Solid State Circuits, 2010
A 345mW heterogeneous many-core processor with an intelligent inference engine for robust object recognition.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010
A 30fps stereo matching processor based on belief propagation with disparity-parallel PE array architecture.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Intelligent NoC with neuro-fuzzy bandwidth regulation for a 51 IP object recognition processor.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010
2009
IEEE Trans. Very Large Scale Integr. Syst., 2009
A Configurable Heterogeneous Multicore Architecture With Cellular Neural Network for Real-Time Object Recognition.
IEEE Trans. Circuits Syst. Video Technol., 2009
Real-Time Object Recognition with Neuro-Fuzzy Controlled Workload-Aware Task Pipelining.
IEEE Micro, 2009
A 125 GOPS 583 mW Network-on-Chip Based Parallel Processor With Bio-Inspired Visual Attention Engine.
IEEE J. Solid State Circuits, 2009
Memory-centric network-on-chip for power efficient execution of task-level pipeline on a multi-core processor.
IET Comput. Digit. Tech., 2009
A 201.4GOPS 496mW real-time multi-object recognition processor with bio-inspired neural perception engine.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009
A 60fps 496mW multi-object recognition processor with workload-aware dynamic power management.
Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009
A 118.4GB/s multi-casting network-on-chip for real-time object recognition processor.
Proceedings of the 35th European Solid-State Circuits Conference, 2009
A 54GOPS 51.8mW analog-digital mixed mode Neural Perception Engine for fast object detection.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009
2008
IEEE J. Solid State Circuits, 2008
IEEE Commun. Mag., 2008
A 125GOPS 583mW Network-on-Chip Based Parallel Processor with Bio-inspired Visual-Attention Engine.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008
Proceedings of the ESSCIRC 2008, 2008
Vision platform for mobile intelligent robot based on 81.6 GOPS object recognition processor.
Proceedings of the 45th Design Automation Conference, 2008
2007
Solutions for Real Chip Implementation Issues of NoC and Their Application to Memory-Centric NoC.
Proceedings of the First International Symposium on Networks-on-Chips, 2007
A 52.4mW 3D Graphics Processor with 141Mvertices/s Vertex Shader and 3 Power Domains of Dynamic Voltage and Frequency Scaling.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007
A Low Power Digital Signal Processor with Adaptive Band Activation for Digital Hearing Aid Chip.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
Proceedings of the 33rd European Solid-State Circuits Conference, 2007
Proceedings of the ACM SIGGRAPH/EUROGRAPHICS Conference on Graphics Hardware 2007, 2007
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007
An 81.6 GOPS Object Recognition Processor Based on NoC and Visual Image Processing Memory.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007
2006
Proceedings of the Tenth IEEE International Symposium on Wearable Computers (ISWC 2006), 2006