Byeong-Gyu Nam

Orcid: 0000-0003-0069-1959

According to our database1, Byeong-Gyu Nam authored at least 27 papers between 2005 and 2021.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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Links

On csauthors.net:

Bibliography

2021
MixedNet: Network Design Strategies for Cost-Effective Quantized CNNs.
IEEE Access, 2021

2020
Compact Mixed-Signal Convolutional Neural Network Using a Single Modular Neuron.
IEEE Trans. Circuits Syst., 2020

2018
Session 13 overview: Machine learning and signal processing: Digital architectures and systems subcommittee.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

Session 2 overview: Processors: Digital architectures and systems subcommittee.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

2017
Session 14 overview: Deep-learning processors.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

Session 3 overview: Digital processors.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

A self-powered always-on vision-based wake-up detector for wearable gesture user interfaces.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017

2016
A low-power real-time hidden Markov model accelerator for gesture user interface on wearable devices.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016

2015
A 27 mW Reconfigurable Marker-Less Logarithmic Camera Pose Estimation Engine for Mobile Augmented Reality Processor.
IEEE J. Solid State Circuits, 2015

2014
Intelligent Network-on-Chip With Online Reinforcement Learning for Portable HD Object Recognition Processor.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014

Highlights of the ISSCC 2013 Processors and High Performance Digital Sessions.
IEEE J. Solid State Circuits, 2014

A 27mW reconfigurable marker-less logarithmic camera pose estimation engine for mobile augmented reality processor.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014

2013
A 57 mW 12.5 µJ/Epoch Embedded Mixed-Mode Neuro-Fuzzy Processor for Mobile Real-Time Object Recognition.
IEEE J. Solid State Circuits, 2013

A high-throughput 16× super resolution processor for real-time object recognition SoC.
Proceedings of the ESSCIRC 2013, 2013

2012
Session 12 overview: Multimedia and communications SoCs: Energy-efficient digital subcommittee.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

2011
Design of "green" high-performance processor circuits.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011

2009
An Embedded Stream Processor Core Based on Logarithmic Arithmetic for a Low-Power 3-D Graphics SoC.
IEEE J. Solid State Circuits, 2009

2008
Power and Area-Efficient Unified Computation of Vector and Elementary Functions for Handheld 3D Graphics Systems.
IEEE Trans. Computers, 2008

Cost-effective low-power graphics processing unit for handheld devices.
IEEE Commun. Mag., 2008

2007
A Low-Power Unified Arithmetic Unit for Programmable Handheld 3-D Graphics Systems.
IEEE J. Solid State Circuits, 2007

A 52.4mW 3D Graphics Processor with 141Mvertices/s Vertex Shader and 3 Power Domains of Dynamic Voltage and Frequency Scaling.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

A Power Management Unit with Continuous Co-Locking of Clock Frequency and Supply Voltage for Dynamic Voltage and Frequency Scaling.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

A low-power vector processor using logarithmic arithmetic for handheld 3d graphics systems.
Proceedings of the 33rd European Solid-State Circuits Conference, 2007

A low-power handheld GPU using logarithmic arithmetic and triple DVFS power domains.
Proceedings of the ACM SIGGRAPH/EUROGRAPHICS Conference on Graphics Hardware 2007, 2007

2006
A 231-MHz, 2.18-mW 32-bit Logarithmic Arithmetic Unit for Fixed-Point 3-D Graphics System.
IEEE J. Solid State Circuits, 2006

2005
Development of a 3-D graphics rendering engine with lighting acceleration for handheld multimedia systems.
IEEE Trans. Consumer Electron., 2005

A fixed-point 3D graphics library with energy-efficient cache architecture for mobile multimedia systems.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005


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