Kwanho Kim

According to our database1, Kwanho Kim authored at least 45 papers between 2000 and 2019.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.



In proceedings 
PhD thesis 




A case-based reasoning approach to fast optimization of travel routes for large-scale AS/RSs.
J. Intelligent Manufacturing, 2019

An Information Retrieval Approach for Robust Prediction of Road Surface States.
Sensors, 2017

A Biological Signal-Based Stress Monitoring Framework for Children Using Wearable Devices.
Sensors, 2017

Next Place Prediction Based on Spatiotemporal Pattern Mining of Mobile Device Logs.
Sensors, 2016

i-RM: An intelligent risk management framework for context-aware ubiquitous cold chain logistics.
Expert Syst. Appl., 2016

Analyzing Information Flow and Context for Facebook Fan Pages.
IEICE Transactions, 2014

An analysis on movement patterns between zones using smart card data in subway networks.
International Journal of Geographical Information Science, 2014

Language independent semantic kernels for short-text classification.
Expert Syst. Appl., 2014

Revenue maximizing itemset construction for online shopping services.
Industrial Management and Data Systems, 2013

Pricing fraud detection in online shopping malls using a finite mixture model.
Electronic Commerce Research and Applications, 2013

Discovery of Information Diffusion Process in Social Networks.
IEICE Transactions, 2012

Bursty event detection from text streams for disaster management.
Proceedings of the 21st World Wide Web Conference, 2012

24-GOPS 4.5-mm2 Digital Cellular Neural Network for Rapid Visual Attention in an Object-Recognition SoC.
IEEE Trans. Neural Networks, 2011

FlowWiki: A wiki based platform for ad hoc collaborative workflows.
Knowl.-Based Syst., 2011

Online Video Recommendation through Tag-Cloud Aggregation.
IEEE MultiMedia, 2011

Semantic Pattern Tree Kernels for Short-Text Classification.
Proceedings of the IEEE Ninth International Conference on Dependable, 2011

Visual Image Processing RAM: Memory Architecture With 2-D Data Location Search and Data Consistency Management for a Multicore Object Recognition Processor.
IEEE Trans. Circuits Syst. Video Techn., 2010

Familiarity based unified visual attention model for fast and robust object recognition.
Pattern Recognition, 2010

A 201.4 GOPS 496 mW Real-Time Multi-Object Recognition Processor With Bio-Inspired Neural Perception Engine.
J. Solid-State Circuits, 2010

A vector space approach to tag cloud similarity ranking.
Inf. Process. Lett., 2010

Searching Social Media Streams on the Web.
IEEE Intelligent Systems, 2010

Characteristics of the Threshold-Based IR-UWB Positioning System.
Proceedings of the 72nd IEEE Vehicular Technology Conference, 2010

81.6 GOPS Object Recognition Processor Based on a Memory-Centric NoC.
IEEE Trans. VLSI Syst., 2009

A Configurable Heterogeneous Multicore Architecture With Cellular Neural Network for Real-Time Object Recognition.
IEEE Trans. Circuits Syst. Video Techn., 2009

A 125 GOPS 583 mW Network-on-Chip Based Parallel Processor With Bio-Inspired Visual Attention Engine.
J. Solid-State Circuits, 2009

Memory-centric network-on-chip for power efficient execution of task-level pipeline on a multi-core processor.
IET Computers & Digital Techniques, 2009

Hyperlinking the work for self-management of flexible workflows.
Commun. ACM, 2009

A 201.4GOPS 496mW real-time multi-object recognition processor with bio-inspired neural perception engine.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009

Selfish retransmission protocol in an IR-UWB system.
Proceedings of the 2009 International Conference on Information Networking, 2009

Cost-effective low-power graphics processing unit for handheld devices.
IEEE Communications Magazine, 2008

A 125GOPS 583mW Network-on-Chip Based Parallel Processor with Bio-inspired Visual-Attention Engine.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

Vision platform for mobile intelligent robot based on 81.6 GOPS object recognition processor.
Proceedings of the 45th Design Automation Conference, 2008

Solutions for Real Chip Implementation Issues of NoC and Their Application to Memory-Centric NoC.
Proceedings of the First International Symposium on Networks-on-Chips, 2007

A 52.4mW 3D Graphics Processor with 141Mvertices/s Vertex Shader and 3 Power Domains of Dynamic Voltage and Frequency Scaling.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

A low-power handheld GPU using logarithmic arithmetic and triple DVFS power domains.
Proceedings of the ACM SIGGRAPH/EUROGRAPHICS Conference on Graphics Hardware 2007, 2007

An 81.6 GOPS Object Recognition Processor Based on NoC and Visual Image Processing Memory.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

A network-on-chip with 3Gbps/wire serialized on-chip interconnect using adaptive control schemes.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

An Integrated Approach to Process-Driven Business Performance Monitoring and Analysis for Real-Time Enterprises.
Proceedings of the Business Intelligence for the Real-Time Enterprises, 2006

A fixed-point 3D graphics library with energy-efficient cache architecture for mobile multimedia systems.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

An arbitration look-ahead scheme for reducing end-to-end latency in networks on chip.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Energy-aware MPEG-4 FGS streaming.
Proceedings of the 40th Design Automation Conference, 2003

Cycle-accurate energy measurement and characterization with a case study of the ARM7TDMI [microprocessors].
IEEE Trans. VLSI Syst., 2002

Energy exploration and reduction of SDRAM memory systems.
Proceedings of the 39th Design Automation Conference, 2002

Cycle-accurate energy consumption measurement and analysis: case study of ARM7TDMI.
Proceedings of the 2000 International Symposium on Low Power Electronics and Design, 2000

Bus encoding for low-power high-performance memory systems.
Proceedings of the 37th Conference on Design Automation, 2000