Joonsoo Kwon
According to our database1,
Joonsoo Kwon
authored at least 9 papers
between 2010 and 2020.
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Bibliography
2020
13.1 A 1Tb 4b/cell NAND Flash Memory with tPROG=2ms, tR=110µs and 1.2Gb/s High-Speed IO Rate.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
2015
Three-Dimensional 128 Gb MLC Vertical nand Flash Memory With 24-WL Stacked Layers and 50 MB/s High-Speed Programming.
IEEE J. Solid State Circuits, 2015
2014
19.5 Three-dimensional 128Gb MLC vertical NAND Flash-memory with 24-WL stacked layers and 50MB/s high-speed programming.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
2012
A 92-mW Real-Time Traffic Sign Recognition System With Robust Illumination Adaptation and Support Vector Machine.
IEEE J. Solid State Circuits, 2012
2011
A 345 mW Heterogeneous Many-Core Processor With an Intelligent Inference Engine for Robust Object Recognition.
IEEE J. Solid State Circuits, 2011
A 92mW real-time traffic sign recognition system with robust light and dark adaptation.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011
2010
A 345mW heterogeneous many-core processor with an intelligent inference engine for robust object recognition.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Intelligent NoC with neuro-fuzzy bandwidth regulation for a 51 IP object recognition processor.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010