Shailendra Sharad

According to our database¹, Shailendra Sharad authored at least 3 papers between 2015 and 2025.

Collaborative distances:

Dijkstra number² of five.
Erdős number³ of four.

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2025

A 38Mb/mm<sup>2</sup> 380/540mV Dual-Rail SRAM in 3nm-FinFET Technology.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Solid-State Circuits Conference, 2025

2019

Allowing Switching off Periphery Voltage Island Instead of Doing it per Instance Through Periphery VDD Collapse in SRAMs.

[BibT_eX]

[DOI]

Proceedings of the 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems, 2019

2015

Two Phase Write Scheme to Improve Low Voltage Write-ability in Medium-Density SRAMs.

[BibT_eX]

[DOI]

M. Sultan M. Siddiqui

Shailendra Sharad

Yogendra Sharma

Amit Khanuja

Proceedings of the 28th International Conference on VLSI Design, 2015

Shailendra Sharad

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