Shailendra Sharad

According to our database, Shailendra Sharad authored at least 3 papers between 2015 and 2025.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2025

A 38Mb/mm² 380/540mV Dual-Rail SRAM in 3nm-FinFET Technology.

Harold Pilo, John Barth, Kapil Dev Dwivedi, Peter Lee, Vikram Kumar, Prasanna Nalawar, Yogeshbhai Patel, Shailendra Sharad, Shakti Singh

Proceedings of the IEEE International Solid-State Circuits Conference, 2025

2019

Allowing Switching off Periphery Voltage Island Instead of Doing it per Instance Through Periphery VDD Collapse in SRAMs.

Krashna Nand Mishra, Ruchin Jain, Shailendra Sharad, Ravindra Shrivastava

Proceedings of the 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems, 2019

2015

Two Phase Write Scheme to Improve Low Voltage Write-ability in Medium-Density SRAMs.

M. Sultan M. Siddiqui, Shailendra Sharad, Yogendra Sharma, Amit Khanuja

Proceedings of the 28th International Conference on VLSI Design, 2015