Harold Pilo

According to our database, Harold Pilo authored at least 11 papers between 2000 and 2013.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2013

A 64Mb SRAM in 22nm SOI technology featuring fine-granularity power gating and low-energy power-supply-partition techniques for 37% leakage reduction.

Harold Pilo, Chad A. Adams, Igor Arsovski, Robert M. Houle, Steve Lamphier, Michael M. Lee, Frank Pavlik, Sushma N. Sambatur, Adnan Seferagic, Richard Wu, Mohammad Imran Younus

Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

2012

A 64 Mb SRAM in 32 nm High-k Metal-Gate SOI Technology With 0.7 V Operation Enabled by Stability, Write-Ability and Read-Ability Enhancements.

Harold Pilo, Igor Arsovski, Kevin Batson, Geordie Braceras, John A. Gabric, Robert M. Houle, Steve Lamphier, Carl Radens, Adnan Seferagic

IEEE J. Solid State Circuits, 2012

2011

A 64Mb SRAM in 32nm High-k metal-gate SOI technology with 0.7V operation enabled by stability, write-ability and read-ability enhancements.

Harold Pilo, Igor Arsovski, Kevin Batson, Geordie Braceras, John A. Gabric, Robert M. Houle, Steve Lamphier, Frank Pavlik, Adnan Seferagic, Liang-Yu Chen, Shang-Bin Ko, Carl Radens

Proceedings of the IEEE International Solid-State Circuits Conference, 2011

2009

An 8 Mb SRAM in 45 nm SOI Featuring a Two-Stage Sensing Scheme and Dynamic Power Management.

Vinod Ramadurai, Harold Pilo, John Andersen, Geordie Braceras, John A. Gabric, Daniel Geise, Steve Lamphier, Yue Tan

IEEE J. Solid State Circuits, 2009

2008

A 450ps Access-Time SRAM Macro in 45nm SOI Featuring a Two-Stage Sensing-Scheme and Dynamic Power Management.

Harold Pilo, Vaidyanathan Ramadurai, Geordie Braceras, John A. Gabric, Steve Lamphier, Yue Tan

Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

2007

An SRAM Design in 65-nm Technology Node Featuring Read and Write-Assist Circuits to Expand Operating Voltage.

Harold Pilo, Charlie Barwin, Geordie Braceras, Chris Browning, Steve Lamphier, Fred Towler

IEEE J. Solid State Circuits, 2007

A 550ps Access-Time Compilable SRAM in 65nm CMOS Technology.

Larry Wissel, Harold Pilo, Chris LeBlanc, Xiaopeng Wang, Steve Lamphier, Michael Fragano

Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

2003

A 5.6-ns random cycle 144-Mb DRAM with 1.4 Gb/s/pin and DDR3-SRAM interface.

Harold Pilo, Darren Anand, John Barth, Steve Burns, Phil Corson, Jim Covino, Steve Lamphier

IEEE J. Solid State Circuits, 2003

2001

Bitline contacts in high density SRAMs: design for testability and stressability.

Harold Pilo, R. Dean Adams, Robert E. Busch, Eric A. Nelson, Geoerge E. Rudgers

Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

2000

An 833-MHz 1.5-W 18-Mb CMOS SRAM with 1.67 Gb/s/pin.

Harold Pilo, Archie Allen, Jim Covino, Patrick Hansen, Steve Lamphier, Chris Murphy, Terry Traver, Pui Yee

IEEE J. Solid State Circuits, 2000

Design-for-test methods for stand-alone SRAMs at 1 Gb/s/pin and beyond.

Harold Pilo, Stu Hall, Patrick Hansen, Steve Lamphier, Chris Murphy

Proceedings of the Proceedings IEEE International Test Conference 2000, 2000