Shaoyi Cheng

According to our database1, Shaoyi Cheng authored at least 13 papers between 2010 and 2017.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2017
Structured Deep Neural Network Pruning via Matrix Pivoting.
CoRR, 2017

Synthesis of program binaries into FPGA accelerators with runtime dependence validation.
Proceedings of the International Conference on Field Programmable Technology, 2017

2016
Accelerator Synthesis and Integration for CPU+FPGA Systems.
PhD thesis, 2016

High Level Synthesis with a Dataflow Architectural Template.
CoRR, 2016

Synthesis of statically analyzable accelerator networks from sequential programs.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

2015
ASTRO: Synthesizing application-specific reconfigurable hardware traces to exploit memory-level parallelism.
Microprocess. Microsystems, 2015

2014
Architectural synthesis of computational pipelines with decoupled memory access.
Proceedings of the 2014 International Conference on Field-Programmable Technology, 2014

2013
Extracting memory-level parallelism through reconfigurable hardware traces.
Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2013

2012
Exploring Many-Core Design Templates for FPGAs and ASICs.
Int. J. Reconfigurable Comput., 2012

Exploiting Memory-Level Parallelism in Reconfigurable Accelerators.
Proceedings of the 2012 IEEE 20th Annual International Symposium on Field-Programmable Custom Computing Machines, 2012

2011
Using many-core architectural templates for FPGA-based computing (abstract only).
Proceedings of the ACM/SIGDA 19th International Symposium on Field Programmable Gate Arrays, 2011

2010
Cascading Deep Pipelines to Achieve High Throughput in Numerical Reduction Operations.
Proceedings of the ReConFig'10: 2010 International Conference on Reconfigurable Computing and FPGAs, 2010

MARC: A Many-Core Approach to Reconfigurable Computing.
Proceedings of the ReConFig'10: 2010 International Conference on Reconfigurable Computing and FPGAs, 2010


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