Vladimir Stojanovic

According to our database1, Vladimir Stojanovic authored at least 138 papers between 1998 and 2022.

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Bibliography

2022
Online reinforcement learning multiplayer non-zero sum games of continuous-time Markov jump linear systems.
Appl. Math. Comput., 2022

2021
Robust PD-type iterative learning control for discrete systems with multiple time-delays subjected to polytopic uncertainty and restricted frequency-domain.
Multidimens. Syst. Signal Process., 2021

JUMBO: Scalable Multi-task Bayesian Optimization using Offline Data.
CoRR, 2021

Finite-time asynchronous dissipative filtering of conic-type nonlinear Markov jump systems.
Sci. China Inf. Sci., 2021

Fully Integrated Electronic-Photonic Ultrasound Receiver Array for Endoscopic Imaging Applications in a Zero-Change 45nm CMOS-SOI Process.
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021




MOSCAP Ring Modulator with 1.5 µm Radius, 8.5 THz FSR and 30 GHz/V Shift Efficiency in a 45 nm SOI CMOS Process.
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2021

Cryo-Compatible, Silicon Spoked-Ring Modulator in a 45nm CMOS Platform for 4K-to-Room-Temperature Optical Links.
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2021

Fully Integrated Electronic-Photonic Sensor for Label-Free Refractive Index Sensing in Advanced Zero-Change CMOS-SOI Process.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2021

2020
A Multicriteria Decision Aid-Based Model for Measuring the Efficiency of Business-Friendly Cities.
Symmetry, 2020

TeraPHY: A Chiplet Technology for Low-Power, High-Bandwidth In-Package Optical I/O.
IEEE Micro, 2020

A Laser-Forwarded Coherent Transceiver in 45-nm SOI CMOS Using Monolithic Microring Resonators.
IEEE J. Solid State Circuits, 2020

An unsupervised fault diagnosis method for rolling bearing using STFT and generative neural networks.
J. Frankl. Inst., 2020

Event-based fuzzy control for T-S fuzzy networked systems with various data missing.
Neurocomputing, 2020

GACEM: Generalized Autoregressive Cross Entropy Method for Multi-Modal Black Box Constraint Satisfaction.
CoRR, 2020

2019
A Differential Optical Receiver With Monolithic Split-Microring Photodetector.
IEEE J. Solid State Circuits, 2019

A 1-mW Class-AB Amplifier With -101 dB THD+N for High-Fidelity 16 $\Omega$ Headphones in 65-nm CMOS.
IEEE J. Solid State Circuits, 2019

A Single-Chip Optical Phased Array in a Wafer-Scale Silicon Photonics/CMOS 3D-Integration Platform.
IEEE J. Solid State Circuits, 2019

Tuning Algorithms and Generators for Efficient Edge Inference.
CoRR, 2019

A Laser-forwarded Coherent 10Gb/s BPSK Transceiver using Monolithic Microring Resonators in 45nm SOI CMOS.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

Fully Integrated Coherent LiDAR in 3D-Integrated Silicon Photonics/65nm CMOS.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

A Single-Chip Optical Phased Array in a 3D-Integrated Silicon Photonics/65nm CMOS Technology.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019

BagNet: Berkeley Analog Generator with Layout Optimizer Boosted with Deep Neural Networks.
Proceedings of the International Conference on Computer-Aided Design, 2019

Design and Characterization of Monolithic Microring Resonator based Photodetector in 45nm SOI CMOS.
Proceedings of the 49th European Solid-State Device Research Conference, 2019

Analog Circuit Generator based on Deep Neural Network enhanced Combinatorial Optimization.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2018
Equivalent Baseband Models and Corresponding Digital Predistortion for Compensating Dynamic Passband Nonlinearities in Phase-Amplitude Modulation-Demodulation Schemes.
IEEE Trans. Signal Process., 2018

MPDCompress - Matrix Permutation Decomposition Algorithm for Deep Neural Network Compression.
CoRR, 2018

A 1MW -101DB THD+N Class-AB High-Fidelity Headphone Driver in 65NM CMOS.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018

A 40GB/S Optical NRZ Transmitter Based on Monolithic Microring Modulators in 45NM SOI CMOS.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018

Microsecond Optical Switching Network of Processor SoCs with Optical I/O.
Proceedings of the Optical Fiber Communications Conference and Exposition, 2018

Monolithic Optical Transceivers in 65 nm Bulk CMOS.
Proceedings of the Optical Fiber Communications Conference and Exposition, 2018

Optimal Spectral Estimation and System Trade-Off in Long-Distance Frequency-Modulated Continuous-Wave Lidar.
Proceedings of the 2018 IEEE International Conference on Acoustics, 2018

A Bandwidth-Dense, Low Power Electronic-Photonic Platform and Architecture for Multi-Tbps Optical I/O.
Proceedings of the European Conference on Optical Communication, 2018

2017
First Principles Optimization of Opto-Electronic Communication Links.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017

A 40-Gb/s PAM-4 Transmitter Based on a Ring-Resonator Optical DAC in 45-nm SOI CMOS.
IEEE J. Solid State Circuits, 2017

Structured Deep Neural Network Pruning via Matrix Pivoting.
CoRR, 2017


29.3 A 40Gb/s PAM-4 transmitter based on a ring-resonator optical DAC in 45nm SOI CMOS.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

2016
A 45 nm CMOS-SOI Monolithic Photonics Platform With Bit-Statistics-Based Resonant Microring Thermal Tuning.
IEEE J. Solid State Circuits, 2016

A Nature Inspired Parameter Tuning Approach to Cascade Control for Hydraulically Driven Parallel Robot Platform.
J. Optim. Theory Appl., 2016

Robust identification of OE model with constrained output using optimal input design.
J. Frankl. Inst., 2016

Depletion-based optical modulators in a bulk 65 nm CMOS platform.
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2016

A 12Gb/s, 8.6µApp input sensitivity, monolithic-integrated fully differential optical receiver in CMOS 45nm SOI process.
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016

Discrete-time models resulting from dynamic continuous-time perturbations in phase-amplitude modulation-demodulation schemes.
Proceedings of the 55th IEEE Conference on Decision and Control, 2016

A model predictive control equalization transmitter for asymmetric interfaces in 28nm FDSOI.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016

2015
Single-chip microprocessor that communicates directly using light.
Nat., 2015

A Monolithically-Integrated Chip-to-Chip Optical Link in Bulk CMOS.
IEEE J. Solid State Circuits, 2015

Baseband Equivalent Models Resulting From Dynamic Continuous-Time Perturbations In Phase-Amplitude Modulation-Demodulation Schemes (Expanded version).
CoRR, 2015

Geometrically nonlinear vibrations of beams supported by a nonlinear elastic foundation with variable discontinuity.
Commun. Nonlinear Sci. Numer. Simul., 2015

Circuits evening panel discussion 1: Is university circuit design research and education keeping up with industry needs?
Proceedings of the Symposium on VLSI Circuits, 2015

A 45nm SOI monolithic photonics chip-to-chip link with bit-statistics-based resonant microring thermal tuning.
Proceedings of the Symposium on VLSI Circuits, 2015

An ultra low power 3D integrated intra-chip silicon electronic-photonic link.
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2015

DELPHI: a framework for RTL-based architecture design evaluation using DSENT models.
Proceedings of the 2015 IEEE International Symposium on Performance Analysis of Systems and Software, 2015

Demonstration of an optical chip-to-chip link in a 3D integrated electronic-photonic platform.
Proceedings of the ESSCIRC Conference 2015, 2015

2014
Model Predictive Control Equalization for High-Speed I/O Links.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014

Adaptive Input Design for Identification of Output Error Model with Constrained Output.
Circuits Syst. Signal Process., 2014

A monolithically-integrated optical transmitter and receiver in a zero-change 45nm SOI process.
Proceedings of the Symposium on VLSI Circuits, 2014

Energy-efficient active photonics in a zero-change, state-of-the-art CMOS process.
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2014

Floating-point unit design with nano-electro-mechanical (NEM) relays.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2014

F1: Digitally assisted analog and analog-assisted digital in high-performance scaled CMOS process.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

27.4 A 0.75-million-point fourier-transform chip for frequency-sparse signals.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

Serbia Forum - Digital Cultural Heritage Portal.
Proceedings of the Image and Signal Processing - 6th International Conference, 2014

A 45nm 1.3GHz 16.7 double-precision GFLOPS/W RISC-V processor with vector accelerators.
Proceedings of the ESSCIRC 2014, 2014

2013
On U-Statistics and Compressed Sensing II: Non-Asymptotic Worst-Case Analysis.
IEEE Trans. Signal Process., 2013

On U-Statistics and Compressed Sensing I: Non-Asymptotic Average-Case Analysis.
IEEE Trans. Signal Process., 2013

Why Analog-to-Information Converters Suffer in High-Bandwidth Sparse Signal Applications.
IEEE Trans. Circuits Syst. I Regul. Pap., 2013

Energy-Aware Design of Compressed Sensing Systems for Wireless Sensors Under Performance and Reliability Constraints.
IEEE Trans. Circuits Syst. I Regul. Pap., 2013

High-Throughput Signal Component Separator for Asymmetric Multi-Level Outphasing Power Amplifiers.
IEEE J. Solid State Circuits, 2013

Resolving poor TCP performance on high-speed long distance links - Overview and comparison of BIC, CUBIC and Hybla.
Proceedings of the IEEE 11th International Symposium on Intelligent Systems and Informatics, 2013

Chip and board-scale integrated Photonic Networks for next-generation computers.
Proceedings of the 2013 Optical Fiber Communication Conference and Exposition and the National Fiber Optic Engineers Conference (OFC/NFOEC), 2013

A 1.23pJ/b 2.5Gb/s monolithically integrated optical carrier-injection ring modulator and all-digital driver circuit in commercial 45nm SOI.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

F2: VLSI power-management techniques: Principles and applications.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

Hardware-Software Codesign for Embedded Numerical Acceleration.
Proceedings of the 21st IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2013

Design trade-offs in signal component separators for outphasing power amplifiers.
Proceedings of the ESSCIRC 2013, 2013

Breaking the energy barrier in fault-tolerant caches for multicore systems.
Proceedings of the Design, Automation and Test in Europe, 2013

Relays do not leak: CMOS does.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

2012
Reliable Ultra-Low-Voltage Cache Design for Many-Core Systems.
IEEE Trans. Circuits Syst. II Express Briefs, 2012

A Monolithically-Integrated Optical Receiver in Standard 45-nm SOI.
IEEE J. Solid State Circuits, 2012

Design and Analysis of a Hardware-Efficient Compressed Sensing Architecture for Data Compression in Wireless Sensors.
IEEE J. Solid State Circuits, 2012

Designing Chip-Level Nanophotonic Interconnection Networks.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2012

DSENT - A Tool Connecting Emerging Photonics with Electronics for Opto-Electronic Networks-on-Chip Modeling.
Proceedings of the 2012 Sixth IEEE/ACM International Symposium on Networks-on-Chip (NoCS), 2012

Power/performance optimization of many-core processor SoCs.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

Cross-layer Energy and Performance Evaluation of a Nanophotonic Manycore Processor System Using Real Application Workloads.
Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium, 2012

Non-asymptotic analysis of compressed sensing random matrices: An U-statistics approach.
Proceedings of IEEE International Conference on Communications, 2012

Performance trade-offs and design limitations of analog-to-information converter front-ends.
Proceedings of the 2012 IEEE International Conference on Acoustics, 2012

2011
Discrete-Time, Linear Periodically Time-Variant Phase-Locked Loop Model for Jitter Analysis.
IEEE Trans. Circuits Syst. I Regul. Pap., 2011

Fully Digital Transmit Equalizer With Dynamic Impedance Modulation.
IEEE J. Solid State Circuits, 2011

Demonstration of Integrated Micro-Electro-Mechanical Relay Circuits for VLSI Applications.
IEEE J. Solid State Circuits, 2011

A 6.25 Gb/s Voltage-Time Conversion Based Fractionally Spaced Linear Receive Equalizer for Mesochronous High-Speed Links.
IEEE J. Solid State Circuits, 2011

Design of "green" high-performance processor circuits.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011

Addressing link-level design tradeoffs for integrated photonic interconnects.
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011

Injection-locked clock receiver for monolithic optical link in 45nm SOI.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011

2010
Guest Editorial for Special Issue on High-Performance Multichip Interconnections.
IEEE Trans. Circuits Syst. II Express Briefs, 2010

Compact Modeling of Nonlinear Analog Circuits Using System Identification via Semidefinite Programming and Incremental Stability Certification.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

An Energy-Efficient Equalized Transceiver for RC-Dominant Channels.
IEEE J. Solid State Circuits, 2010

Silicon 3D-integration technology and systems.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

Signal and power integrity for SoCs.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

Demonstration of integrated micro-electro-mechanical switch circuits for VLSI applications.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

Re-architecting DRAM memory systems with monolithically integrated silicon photonics.
Proceedings of the 37th International Symposium on Computer Architecture (ISCA 2010), 2010

Digital link pre-emphasis with dynamic driver impedance modulation.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

Analysis and demonstration of MEM-relay power gating.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

A low-power area-efficient switching scheme for charge-sharing DACs in SAR ADCs.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

A signal-agnostic compressed sensing acquisition system for wireless and implantable sensors.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

2009
Building Many-Core Processor-to-DRAM Networks with Monolithic CMOS Silicon Photonics.
IEEE Micro, 2009

A Modeling and exploration framework for interconnect network design in the nanometer era.
Proceedings of the Third International Symposium on Networks-on-Chips, 2009

Silicon-photonic clos networks for global on-chip communication.
Proceedings of the Third International Symposium on Networks-on-Chips, 2009

A 4Gb/s/ch 356fJ/b 10mm equalized on-chip interconnect with nonlinear charge-injecting transmit filter and transimpedance receiver in 90nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009

Designing multi-socket systems using silicon photonics.
Proceedings of the 23rd international conference on Supercomputing, 2009

Designing Energy-Efficient Low-Diameter On-Chip Networks with Equalized Interconnects.
Proceedings of the 17th IEEE Symposium on High Performance Interconnects, 2009

An oscilloscope array for high-impedance device characterization.
Proceedings of the 35th European Solid-State Circuits Conference, 2009

Yield-driven iterative robust circuit optimization algorithm.
Proceedings of the 46th Design Automation Conference, 2009

Discrete-time, cyclostationary phase-locked loop model for jitter analysis.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009

2008
Near-Optimal Equalizer and Timing Adaptation for I/O Links Using a BER-Based Metric.
IEEE J. Solid State Circuits, 2008

A 24 Gb/s Software Programmable Analog Multi-Tone Transmitter.
IEEE J. Solid State Circuits, 2008

Characterization of Equalized and Repeated Interconnects for NoC Applications.
IEEE Des. Test Comput., 2008

Optimization-based framework for simultaneous circuit-and-system design-space exploration: a high-speed link example.
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

Integrated circuit design with NEM relays.
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

Low-Complexity Pattern-Eliminating Codes for ISI-Limited Channels.
Proceedings of IEEE International Conference on Communications, 2008

Building Manycore Processor-to-DRAM Networks with Monolithic Silicon Photonics.
Proceedings of the 16th Annual IEEE Symposium on High Performance Interconnects (HOTI 2008), 2008

2007
Scaling and evaluation of carbon nanotube interconnects for VLSI applications.
Proceedings of the 2nd Internationa ICST Conference on Nano-Networks, 2007

A 7.5Gb/s 10-Tap DFE Receiver with First Tap Partial Response, Spectrally Gated Adaptation, and 2nd-Order Data-Filtered CDR.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

Equalized interconnects for on-chip networks: modeling and optimization framework.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

Statistical Simulator for Block Coded Channels with Long Residual Interference.
Proceedings of IEEE International Conference on Communications, 2007

Practical Limits of Multi-Tone Signaling Over High-Speed Backplane Electrical Links.
Proceedings of IEEE International Conference on Communications, 2007

2006
Analog Multi-Tone Signaling for High-Speed Backplane Electrical Links.
Proceedings of the Global Telecommunications Conference, 2006. GLOBECOM '06, San Francisco, CA, USA, 27 November, 2006

A cost-effective implementation of an ECC-protected instruction queue for out-of-order microprocessors.
Proceedings of the 43rd Design Automation Conference, 2006

Power-centric design of high-speed I/Os.
Proceedings of the 43rd Design Automation Conference, 2006

2005
High-Speed Serial Links: Design Trends and Challenges, invited.
Proceedings of the 5th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC 2005), 2005

Modeling, simulation, and design of a multi-mode 2-10 Gb/sec fully adaptive serial link system.
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

2004
Optimal linear precoding with theoretical and practical data rates in high-speed serial-link backplane communication.
Proceedings of IEEE International Conference on Communications, 2004

Multi-tone signaling for high-speed backplane electrical links.
Proceedings of the Global Telecommunications Conference, 2004. GLOBECOM '04, Dallas, Texas, USA, 29 November, 2004

Equalization of modal dispersion in multimode fiber using spatial light modulators.
Proceedings of the Global Telecommunications Conference, 2004. GLOBECOM '04, Dallas, Texas, USA, 29 November, 2004

2002
Methods for true power minimization.
Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002

Transmit pre-emphasis for high-speed time-division-multiplexed serial-link transceiver.
Proceedings of the IEEE International Conference on Communications, 2002

1998
A unified approach in the analysis of latches and flip-flops for low-power systems.
Proceedings of the 1998 International Symposium on Low Power Electronics and Design, 1998

Comparative analysis of latches and flip-flops for high-performance systems.
Proceedings of the International Conference on Computer Design: VLSI in Computers and Processors, 1998


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