Rawan Naous

According to our database, Rawan Naous authored at least 17 papers between 2007 and 2022.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2022

A 5-nm 254-TOPS/W 221-TOPS/mm² Fully-Digital Computing-in-Memory Macro Supporting Wide-Range Dynamic-Voltage-Frequency Scaling and Simultaneous MAC and Write Operations.

Hidehiro Fujiwara, Haruki Mori, Wei-Chang Zhao, Mei-Chen Chuang, Rawan Naous, Chao-Kai Chuang, Takeshi Hashizume, Dar Sun, Chia-Fu Lee, Kerem Akarvardar, Saman Adham, Tan-Li Chou, Mahmut Ersin Sinangil, Yih Wang, Yu-Der Chih, Yen-Huei Chen, Hung-Jen Liao, Tsung-Yung Jonathan Chang

Proceedings of the IEEE International Solid-State Circuits Conference, 2022

2021

A 7-nm Compute-in-Memory SRAM Macro Supporting Multi-Bit Input, Weight and Output and Achieving 351 TOPS/W and 372.4 GOPS.

Mahmut E. Sinangil, Burak Erbagci, Rawan Naous, Kerem Akarvardar, Dar Sun, Win-San Khwa, Hung-Jen Liao, Yih Wang, Jonathan Chang

IEEE J. Solid State Circuits, 2021

An 89TOPS/W and 16.3TOPS/mm² All-Digital SRAM-Based Full-Precision Compute-In Memory Macro in 22nm for Machine-Learning Edge Applications.

Yu-Der Chih, Po-Hao Lee, Hidehiro Fujiwara, Yi-Chun Shih, Chia-Fu Lee, Rawan Naous, Yu-Lin Chen, Chieh-Pu Lo, Cheng-Han Lu, Haruki Mori, Wei-Cheng Zhao, Dar Sun, Mahmut E. Sinangil, Yen-Huei Chen, Tan-Li Chou, Kerem Akarvardar, Hung-Jen Liao, Yih Wang, Meng-Fan Chang, Tsung-Yung Jonathan Chang

Proceedings of the IEEE International Solid-State Circuits Conference, 2021

2019

Tuning Algorithms and Generators for Efficient Edge Inference.

Rawan Naous, Lazar Supic, Yoonhwan Kang, Ranko Seradejovic, Anish Singhani, Vladimir Stojanovic

CoRR, 2019

Approximate Computing With Stochastic Transistors' Voltage Over-Scaling.

Ren Li, Rawan Naous, Hossein Fariborzi, Khaled Nabil Salama

IEEE Access, 2019

2018

MPDCompress - Matrix Permutation Decomposition Algorithm for Deep Neural Network Compression.

Lazar Supic, Rawan Naous, Ranko Sredojevic, Aleksandra Faust, Vladimir Stojanovic

CoRR, 2018

2017

Structured Deep Neural Network Pruning via Matrix Pivoting.

Ranko Sredojevic, Shaoyi Cheng, Lazar Supic, Rawan Naous, Vladimir Stojanovic

CoRR, 2017

Design and analysis of 2T-2M Ternary content addressable memories.

Mohamed A. Bahloul, Mohamed E. Fouda, Rawan Naous, M. Affan Zidan, Ahmed M. Eltawil, Fadi J. Kurdahi, Khaled Nabil Salama

Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

Hardware emulation of Memristor based Ternary Content Addressable Memory.

Mohamed A. Bahloul, Rawan Naous, Mohamed Slim Masmoudi

Proceedings of the 14th International Multi-Conference on Systems, 2017

2016

Pilot assisted readout for passive memristor crossbars.

Rawan Naous, Mohammed Affan Zidan, Ahmed K. Sultan, Khaled Nabil Salama

Microelectron. J., 2016

Statistical Analysis for Memristor Crossbar Memories.

Rawan Naous, Mohammed Affan Zidan, Ahmed K. Sultan, Khaled Nabil Salama

Int. J. Unconv. Comput., 2016

Stochastic synaptic plasticity with memristor crossbar arrays.

Rawan Naous, Maruan Al-Shedivat, Emre Neftci, Gert Cauwenberghs, Khaled Nabil Salama

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

gTBS: A green Task-Based Sensing for energy efficient Wireless Sensor Networks.

Abdullah Alhalafi, Lokman Sboui, Rawan Naous, Basem Shihada

Proceedings of the IEEE Conference on Computer Communications Workshops, 2016

Channel equalization techniques for non-volatile memristor memories.

Rawan Naous, Mohammed Affan Zidan, Ahmed K. Sultan, Khaled Nabil Salama

Proceedings of the 2016 Annual Conference on Information Science and Systems, 2016

2015

Memristors Empower Spiking Neurons With Stochasticity.

Maruan Al-Shedivat, Rawan Naous, Gert Cauwenberghs, Khaled Nabil Salama

IEEE J. Emerg. Sel. Topics Circuits Syst., 2015

Inherently stochastic spiking neurons for probabilistic neural computation.

Maruan Al-Shedivat, Rawan Naous, Emre Neftci, Gert Cauwenberghs, Khaled N. Salama

Proceedings of the 7th International IEEE/EMBS Conference on Neural Engineering, 2015

2007

A Configurable Multi-ported Register File Architecture for Soft Processor Cores.

Mazen A. R. Saghir, Rawan Naous

Proceedings of the Reconfigurable Computing: Architectures, 2007