Sukarn Agarwal

Orcid: 0000-0003-1292-3235

According to our database1, Sukarn Agarwal authored at least 22 papers between 2016 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2023
DELICIOUS: Deadline-Aware Approximate Computing in Cache-Conscious Multicore.
IEEE Trans. Parallel Distributed Syst., February, 2023

Compound Memory Models.
Proc. ACM Program. Lang., 2023

Architecting Selective Refresh based Multi-Retention Cache for Heterogeneous System (ARMOUR).
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

2021
Improving the Performance of Hybrid Caches Using Partitioned Victim Caching.
ACM Trans. Embed. Comput. Syst., 2021

DAMUS: Dynamic Allocation based on Write Frequency in MUlti-Retention STT-RAM based Last Level Caches.
Proceedings of the 22nd International Symposium on Quality Electronic Design, 2021

ABACa: Access Based Allocation on Set Wise Multi-Retention in STT-RAM Last Level Cache.
Proceedings of the 32nd IEEE International Conference on Application-specific Systems, 2021

2020
Reuse Distance-based Victim Cache for Effective Utilisation of Hybrid Main Memory System.
ACM Trans. Design Autom. Electr. Syst., 2020

LiNoVo: Longevity Enhancement of Non-Volatile Last Level Caches in Chip Multiprocessors.
Proceedings of the 2020 IEEE Computer Society Annual Symposium on VLSI, 2020

DidaSel: dirty data based selection of VC for effective utilization of NVM buffers in on-chip interconnects.
Proceedings of the ISLPED '20: ACM/IEEE International Symposium on Low Power Electronics and Design, 2020

2019
Improving the Lifetime of Non-Volatile Cache by Write Restriction.
IEEE Trans. Computers, 2019

Towards Optimizing Refresh Energy in embedded-DRAM Caches using Private Blocks.
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019

Enhancing the Lifetime of Non-Volatile Caches by Exploiting Module-Wise Write Restriction.
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019

2018
Reuse-Distance-Aware Write-Intensity Prediction of Dataless Entries for Energy-Efficient Hybrid Caches.
IEEE Trans. Very Large Scale Integr. Syst., 2018

Fault Tolerance in Network on Chip Using Bypass Path Establishing Packets.
Proceedings of the 31st International Conference on VLSI Design and 17th International Conference on Embedded Systems, 2018

Towards Analysing the Effect of Hybrid Caches on the Temperature of Tiled Chip Multi-Processors.
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2018

Non-blocking Gated Buffers for Energy Efficient on-chip Interconnects in the era of Dark Silicon.
Proceedings of the 8th International Symposium on Embedded Computing and System Design, 2018

Towards Analysing the Effect of Snoozy Caches on the Temperature of Tiled Chip Multi-Processors.
Proceedings of the 8th International Symposium on Embedded Computing and System Design, 2018

2017
Towards a Better Lifetime for Non-volatile Caches in Chip Multiprocessors.
Proceedings of the 30th International Conference on VLSI Design and 16th International Conference on Embedded Systems, 2017

Lifetime Enhancement of Non-Volatile Caches by Exploiting Dynamic Associativity Management Techniques.
Proceedings of the VLSI-SoC: Opportunities and Challenges Beyond the Internet of Things, 2017

Targeting inter set write variation to improve the lifetime of non-volatile cache using fellow sets.
Proceedings of the 2017 IFIP/IEEE International Conference on Very Large Scale Integration, 2017

2016
Restricting writes for energy-efficient hybrid cache in multi-core architectures.
Proceedings of the 2016 IFIP/IEEE International Conference on Very Large Scale Integration, 2016

Towards a dynamic associativity enabled write prediction based hybrid cache.
Proceedings of the 20th International Symposium on VLSI Design and Test, 2016


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