Shigeng Zhao

According to our database, Shigeng Zhao authored at least 4 papers between 2025 and 2026.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2026

A 1.8-ns, 45fJ/bit Time-Domain Sensing Scheme with Offset-Cancelled Resistance-to-Time Converter and 10^-5 BER for Digital RRAM Compute-in-Memory.

Shigeng Zhao, Hao Ding, Yunfan Yang, Jinshan Li, Zhuoya Chen, Xing Zhang, Zongwei Wang, Yimao Cai

Proceedings of the IEEE International Symposium on Circuits and Systems, 2026

A Sparsity-Aware Reconfigurable Sensing-Quantization Circuit for RRAM-Based Analog Compute-in-Memory.

Zhuoya Chen, Hao Ding, Yunfan Yang, Haisu Zhang, Jinshan Li, Shigeng Zhao, Yunyi Fu, Zongwei Wang, Yimao Cai

Proceedings of the IEEE International Symposium on Circuits and Systems, 2026

2025

HRC-CIM: Hybrid RRAM-Capacitor Cell based Compute-in-Memory with High Linearity, Parallelism and Energy Efficiency.

Jinshan Li, Zongwei Wang, Hao Ding, Yunfan Yang, Shigeng Zhao, Shengyu Bao, Jingwei Sun, Ruiqing Xie, Zhuoya Chen, Yimao Cai, Ru Huang

Proceedings of the IEEE International Symposium on Circuits and Systems, 2025

SA-CIM: A 28nm 16Mb RRAM-based Sparsity-Aware Compute-In-Memory Macro for Edge AI Algorithm Processing.

Hao Ding, Zongwei Wang, Jinshan Li, Shigeng Zhao, Heting Gao, Junbo Ao, Ling Liang, Yimao Cai, Ru Huang

Proceedings of the IEEE International Symposium on Circuits and Systems, 2025