Zongwei Wang

Orcid: 0000-0001-6297-2700

Affiliations:

Peking University, Institute of Microelectronics, Beijing, China (PhD 2018)

According to our database¹, Zongwei Wang authored at least 47 papers between 2015 and 2026.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

Timeline

Legend:

Book In proceedings Article PhD thesis Dataset Other

Bibliography

2026

DynaGraph: Lightweight Multi-Model Interaction Framework via Dynamic Topological Reconfiguration.

[BibT_eX]

[DOI]

CoRR, May, 2026

NASiC: 3D NAND-based CAM-Selected Multibit CIM Architecture for Efficient On-Device Mixture-of-Experts LLM Inference.

[BibT_eX]

[DOI]

CoRR, May, 2026

Do Less, Achieve More: Do We Need Every-Step Optimization for RL Fine-tuning of Diffusion Models?

[BibT_eX]

[DOI]

CoRR, May, 2026

Efficient LoRA-Based Weight Update Write-Back in 3D NAND Flash for Large Language Models.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2026

A 1.8-ns, 45fJ/bit Time-Domain Sensing Scheme with Offset-Cancelled Resistance-to-Time Converter and 10-5 BER for Digital RRAM Compute-in-Memory.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2026

RRAM-based CAM for Energy-Efficient In-Memory Text Compression System.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2026

An IZO-Based 2T0C Compute-in-Memory Array with Adaptive Read Voltage Boosting for Energy-Efficient Edge AI.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2026

A Sparsity-Aware Reconfigurable Sensing-Quantization Circuit for RRAM-Based Analog Compute-in-Memory.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2026

SONIC: Smart Optimization for Neural-Integrated CMP with Timing-Aware Fills.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference, 2026

GMaC: NvCIM Architecture for Parallel Point-based Point Cloud Acceleration via Geometric Mapping and Address-Index Computation.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference, 2026

CHIP-MAP: A Collaborative Optimization Framework for Macro Placement Using Large Language Models.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference, 2026

2025

Matrix: Multi-Cipher Structures Dataflow for Parallel and Pipelined TFHE Accelerator.

[BibT_eX]

[DOI]

ACM Trans. Archit. Code Optim., September, 2025

Polynomial geometric transformation based on IGZO charge trapping RAM array for machine vision calibration.

[BibT_eX]

[DOI]

Sci. China Inf. Sci., 2025

PROMPT: Prediction Model for RRAM Programming Optimized by Adaptive Mechanism and Progressive Continuous Transformation.

[BibT_eX]

[DOI]

Proceedings of the 7th ACM/IEEE Symposium on Machine Learning for CAD, 2025

HRC-CIM: Hybrid RRAM-Capacitor Cell based Compute-in-Memory with High Linearity, Parallelism and Energy Efficiency.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2025

SA-CIM: A 28nm 16Mb RRAM-based Sparsity-Aware Compute-In-Memory Macro for Edge AI Algorithm Processing.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2025

Investigation and Mitigation of Transistor Induced Reliability Issues in 40NM RRAM Array.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Reliability Physics Symposium, 2025

Investigation on Temperature-Dependent Resistance States of 40nm MLC-RRAM Macro.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Reliability Physics Symposium, 2025

High-parallel In-memory Data Sorting based on 40nm Analog RRAM Chip.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Memory Workshop, 2025

2024

An RRAM-Based Hierarchical Computing-in-Memory Architecture With Synchronous Parallelism for 3-D Point Cloud Recognition.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, October, 2024

CopyLens: Dynamically Flagging Copyrighted Sub-Dataset Contributions to LLM Outputs.

[BibT_eX]

[DOI]

CoRR, 2024

Investigation and mitigation of Mott neuronal oscillation fluctuation in spiking neural network.

[BibT_eX]

[DOI]

Sci. China Inf. Sci., 2024

An isolated symmetrical 2T2R cell enabling high precision and high density for RRAM-based in-memory computing.

[BibT_eX]

[DOI]

Sci. China Inf. Sci., 2024

A cascaded timestamp-free event camera image compression method for gesture recognition.

[BibT_eX]

[DOI]

Proceedings of the 33rd IEEE International Symposium on Industrial Electronics, 2024

ASAP: An Efficient and Reliable Programming Algorithm for Multi-level RRAM Cell.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Reliability Physics Symposium, 2024

Amorphous InAIZnO-based 2T0C Unit for Peak Signal Detection.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Integrated Circuits, 2024

Ultrafast Pulse Signal Detection Based on a Dual-transistor Structure.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Integrated Circuits, 2024

Invited Paper: Design of an RRAM In-Memory Computing Scheme for Target Tracking Applications.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Integrated Circuits, 2024

2023

Mnemonic Dictionary Learning for Intrinsic Motivation in Reinforcement Learning.

[BibT_eX]

[DOI]

Proceedings of the International Joint Conference on Neural Networks, 2023

Design Considerations of Multi-Level 1S1R Cell for In-Memory Computing.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Integrated Circuits, 2023

A High-Throughput and Configurable TRNG Based on Dual-Mode Memristor for Stochastic Computing.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Integrated Circuits, 2023

Device-Architecture Co-optimization for RRAM-based In-memory Computing.

[BibT_eX]

[DOI]

Proceedings of the 15th IEEE International Conference on ASIC, 2023

2022

PIMulator-NN: An Event-Driven, Cross-Level Simulation Framework for Processing-In-Memory-Based Neural Network Accelerators.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

In Materia Neuron Spiking Plasticity for Sequential Event Processing Based on Dual-Mode Memristor.

[BibT_eX]

[DOI]

Adv. Intell. Syst., 2022

2021

A High Accuracy Multiple-Command Speech Recognition ASIC Based on Configurable One-Dimension Convolutional Neural Network.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

2020

Rotational Pattern Recognition by Spiking Correlated Neural Network Based on Dual-Gated MoS 2 Neuristor.

[BibT_eX]

[DOI]

Adv. Intell. Syst., 2020

MobiLattice: A Depth-wise DCNN Accelerator with Hybrid Digital/Analog Nonvolatile Processing-In-Memory Block.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

Lattice: An ADC/DAC-less ReRAM-based Processing-In-Memory Architecture for Accelerating Deep Convolution Neural Networks.

[BibT_eX]

[DOI]

Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

2019

Investigation of NbOx-based volatile switching device with self-rectifying characteristics.

[BibT_eX]

[DOI]

Sci. China Inf. Sci., 2019

Enhance the Robustness to Time Dependent Variability of ReRAM-Based Neuromorphic Computing Systems with Regularization and 2R Synapse.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

2018

Integration of biocompatible organic resistive memory and photoresistor for wearable image sensing application.

[BibT_eX]

[DOI]

Sci. China Inf. Sci., 2018

Hiearchical Crossbar Design for ReRAM based Write Variation Inhibition on-chip learning.

[BibT_eX]

[DOI]

Proceedings of the Non-Volatile Memory Technology Symposium, 2018

Margin Dependence on Array Size for Asymmetric Resistive Memory Cell.

[BibT_eX]

[DOI]

Proceedings of the Non-Volatile Memory Technology Symposium, 2018

Enhancement of HfO2 Based RRAM Performance Through Hexagonal Boron Nitride Interface Layer.

[BibT_eX]

[DOI]

Proceedings of the Non-Volatile Memory Technology Symposium, 2018

2017

A neural network circuit with associative learning and forgetting process based on memristor neuromorphic device.

[BibT_eX]

[DOI]

Proceedings of the 12th IEEE International Conference on ASIC, 2017

2016

A 3D multi-layer CMOS-RRAM accelerator for neural network.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE International 3D Systems Integration Conference, 2016

2015

Influence of selector-introduced compliance current on HfOx RRAM switching operation.

[BibT_eX]

[DOI]

Proceedings of the 15th Non-Volatile Memory Technology Symposium, 2015

Zongwei Wang

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Bibliography

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