Shimpei Kayano

According to our database, Shimpei Kayano authored at least 6 papers between 1989 and 1991.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

1991

A 45-ns 64-Mb DRAM with a merged match-line test architecture.

Shigeru Mori, Hiroshi Miyamoto, Yoshikazu Morooka, Shigeru Kikuda, Makoto Suwa, Mitsuya Kinoshita, Atsushi Hachisuka, Hideaki Arima, Michihiro Yamada, Tsutomu Yoshihara, Shimpei Kayano

IEEE J. Solid State Circuits, November, 1991

A 5-ns GaAs 16-kb SRAM.

Shuichi Matsue, Hiroshi Makino, Minoru Noda, Hirofumi Nakano, Satoshi Takano, Kazuo Nishitani, Shimpei Kayano

IEEE J. Solid State Circuits, October, 1991

A 7 ns 1 Mb BiCMOS ECL SRAM with shift redundancy.

Atsushi Ohba, Shigeki Ohbayashi, Toru Shiomi, Satoshi Takano, Kenji Anami, Hiroki Honda, Yoshiyuki Ishigaki, Masahiro Hatanaka, Shigeo Nagao, Shimpei Kayano

IEEE J. Solid State Circuits, April, 1991

A self-learning neural network chip with 125 neurons and 10 K self-organization synapses.

Yutaka Arima, Koichiro Mashiko, Keisuke Okada, Tsuyoshi Yamada, Atsushi Maeda, Harufusa Kondoh, Shimpei Kayano

IEEE J. Solid State Circuits, April, 1991

1990

A 7-ns/850-mW GaAs 4-kb SRAM with little dependence on temperature.

Hiroshi Makino, Shuichi Matsue, Minoru Noda, Noriyuki Tanino, Satoshi Takano, Kazuo Nishitani, Shimpei Kayano

IEEE J. Solid State Circuits, October, 1990

1989

Improvement of soft-error rate in MOS SRAMs.

Shuji Murakami, Katsuki Ichinose, Kenji Anami, Shimpei Kayano

IEEE J. Solid State Circuits, August, 1989