Kozo Kinoshita

According to our database1, Kozo Kinoshita authored at least 114 papers between 1970 and 2013.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Awards

IEEE Fellow

IEEE Fellow 1995, "For contributions to testing methods for memory and logic circuits.".

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2013
SAT-Based Test Generation for Open Faults Using Fault Excitation Caused by Effect of Adjacent Lines.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013

2010
Current-based testable design of level shifters in liquid crystal display drivers.
Proceedings of the 15th European Test Symposium, 2010

2008
Low Capture Switching Activity Test Generation for Reducing IR-Drop in At-Speed Scan Testing.
J. Electron. Test., 2008

2007
A statistical error model for image sensors and its testing.
Systems and Computers in Japan, 2007

A Novel ATPG Method for Capture Power Reduction during Scan Testing.
IEICE Trans. Inf. Syst., 2007

2006
A New Method for Low-Capture-Power Test Generation for Scan Testing.
IEICE Trans. Inf. Syst., 2006

A Per-Test Fault Diagnosis Method Based on the <i>X</i>-Fault Model.
IEICE Trans. Inf. Syst., 2006

A New ATPG Method for Efficient Capture Power Reduction During Scan Testing.
Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006

2005
Fault Diagnosis of Physical Defects Using Unknown Behavior Model.
J. Comput. Sci. Technol., 2005

On Design for I<sub>DDQ</sub>-Based Diagnosability of CMOS Circuits Using Multiple Power Supplies.
IEICE Trans. Inf. Syst., 2005

Reducing Scan Shifts Using Configurations of Compatible and Folding Scan Trees.
J. Electron. Test., 2005

On Low-Capture-Power Test Generation for Scan Testing.
Proceedings of the 23rd IEEE VLSI Test Symposium (VTS 2005), 2005

Low-capture-power test generation for scan-based at-speed testing.
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

2004
On per-test fault diagnosis using the X-fault model.
Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

On Configuring Scan Trees to Reduce Scan Shifts based on a Circuit Structure.
Proceedings of the 2nd IEEE International Workshop on Electronic Design, 2004

2003
Channel Width Test Data Compression under a Limited Number of Test Inputs and Outputs.
Proceedings of the 16th International Conference on VLSI Design (VLSI Design 2003), 2003

Reducing Scan Shifts Using Folding Scan Trees.
Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003

Fault Diagnosis for Physical Defects of Unknown Behaviors.
Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003

A BIST Circuit for IDDQ Tests.
Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003

2002
Built-in Self-Test for crosstalk faults in a digital VLSI.
Systems and Computers in Japan, 2002

Foreword.
J. Electron. Test., 2002

On Testing of Interconnect Open Defects in Combinational Logic Circuits with Stems of Large Fanout.
Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

Fault Simulation Method for Crosstalk Faults in Clock-Delayed Domino CMOS Circuits.
Proceedings of the 1st IEEE International Workshop on Electronic Design, 2002

Crosstalk Fault Reduction and Simulation for Clock-Delayed Domino Circuits.
Proceedings of the 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002

2001
IDDQ Sensing Technique for High Speed IDDQ Testing.
Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001

Built-in Self-Test for State Faults Induced by Crosstalk in Sequential Circuits.
Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001

2000
Static test compaction for IDDQ testing of bridging faults in sequential circuits.
Systems and Computers in Japan, 2000

Compaction of IDDQ Test Sequence Using Reassignment Method.
J. Electron. Test., 2000

Algorithms to Select IDDQ Measurement Vectors for Bridging Faults in Sequential Circuits.
J. Electron. Test., 2000

Test Transformation to Improve Compaction by Statistical Encoding.
Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000

Precise test generation for resistive bridging faults of CMOS combinational circuits.
Proceedings of the Proceedings IEEE International Test Conference 2000, 2000

Memory reduction of I/sub DDQ/ test compaction for internal and external bridging faults.
Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000

Simulation of resistive bridging fault to minimize the presence of intermediate voltage and oscillation in CMOS circuits.
Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000

Test sequence compaction for sequential circuits with reset states.
Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000

A high-speed IDDQ sensor implementation.
Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000

Fault models and test generation for IDDQ testing: embedded tutorial.
Proceedings of ASP-DAC 2000, 2000

1999
Efficient Techniques for Reducing IDDQ Observation Time for Sequential Circuits.
Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999

On Test Generation with A Limited Number of Tests.
Proceedings of the 9th Great Lakes Symposium on VLSI (GLS-VLSI '99), 1999

IDDQ Current Dependency on Test Vectors and Bridging Resistance.
Proceedings of the 8th Asian Test Symposium (ATS '99), 1999

Procedure to Overcome the Byzantine General's Problem for Bridging Faults in CMOS Circuits.
Proceedings of the 8th Asian Test Symposium (ATS '99), 1999

On an Effective Selection of IDDQ Measurement Vectors for Sequential Circuits.
Proceedings of the 8th Asian Test Symposium (ATS '99), 1999

Fault Simulation Techniques to Reduce IDDQ Measurement Vectors for Sequential Circuits.
Proceedings of the 8th Asian Test Symposium (ATS '99), 1999

1998
Undetectable Fault Removal of Sequential Circuits Based on Unreachable States.
Proceedings of the 16th IEEE VLSI Test Symposium (VTS '98), 28 April, 1998

Design for Diagnosability of CMOS Circuits.
Proceedings of the 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, 1998

Built-In Self-Test for Multiple CLB Faults of a LUT Type FPGA.
Proceedings of the 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, 1998

An Efficient Procedure for Obtaining Implication Relations and Its Application to Redundancy Identification.
Proceedings of the 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, 1998

Observation Time Reduction for IDDQ Testing of Briding Faults in Sequential Circuits.
Proceedings of the 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, 1998

A High-Speed IDDQ Sensor for Low-Voltage ICs.
Proceedings of the 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, 1998

1997
A diagnosis method for single logic design errors in gate-level combinational circuits.
Systems and Computers in Japan, 1997

I<sub>DDQ</sub> test vector selection for transistor short fault testing.
Systems and Computers in Japan, 1997

On invariant implication relations for removing partial circuits.
Systems and Computers in Japan, 1997

Synthesis of Sequential Circuits by Redundancy Removal and Retiming.
J. Electron. Test., 1997

A Method for Identifying Robust Dependent and Functionally Unsensitizable Paths.
Proceedings of the 10th International Conference on VLSI Design (VLSI Design 1997), 1997

Design of partially parallel scan chain.
Proceedings of the European Design and Test Conference, 1997

An Algorithmic Test Generation Method for Crosstalk Faults in Synchronous Sequential Circuits.
Proceedings of the 6th Asian Test Symposium (ATS '97), 17-18 November 1997, 1997

On Acceleration of Logic Circuits Optimization Using Implication Relations.
Proceedings of the 6th Asian Test Symposium (ATS '97), 17-18 November 1997, 1997

1996
A Fault Simulation Method for Crosstalk Faults in Synchronous Sequential Circuits.
Proceedings of the Digest of Papers: FTCS-26, 1996

Partially Parallel Scan Chain for Test Length Reduction by Using Retiming Technique.
Proceedings of the 5th Asian Test Symposium (ATS '96), 1996

1995
Cost-effective generation of minimal test sets for stuck-at faults in combinational logic circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995

Evaluation of the maximum number of switching gates for CMOS circuits.
Systems and Computers in Japan, 1995

Test pattern generation for crosstalk faults considering the gate delay.
Systems and Computers in Japan, 1995

Retiming for Sequential Circuits with a Specified Initial State and Its Application to Testability Enhancement.
IEICE Trans. Inf. Syst., 1995

Testing of <i>k</i>-FR Circuits under Highly Observable Condition.
IEICE Trans. Inf. Syst., 1995

Efficient Guided-Probe Fault Location Method for Sequential Circuits.
IEICE Trans. Inf. Syst., 1995

Acceleration Techniques of Multiple Fault Test Generation Using Vector Pair Analysis.
IEICE Trans. Inf. Syst., 1995

Partial scan design and test sequence generation based on reduced scan shift method.
J. Electron. Test., 1995

Resynthesis for sequential circuits designed with a specified initial state.
Proceedings of the 13th IEEE VLSI Test Symposium (VTS'95), April 30, 1995

Synthesis for Testability by Sequential Redundancy Removal Using Retiming.
Proceedings of the Digest of Papers: FTCS-25, 1995

Transistor leakage fault location with ZDDQ measurement.
Proceedings of the 4th Asian Test Symposium (ATS '95), 1995

Low power design and its testability.
Proceedings of the 4th Asian Test Symposium (ATS '95), 1995

Test sequence compaction by reduced scan shift and retiming.
Proceedings of the 4th Asian Test Symposium (ATS '95), 1995

1994
An approach to the analysis and detection of crosstalk faults in digital VLSI circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994

On compacting test sets by addition and removal of test vectors.
Proceedings of the 12th IEEE VLSI Test Symposium (VTS'94), 1994

Reduced Scan Shift: A New Testing Method for Sequential Circuit.
Proceedings of the Proceedings IEEE International Test Conference 1994, 1994

A Case Study of Mixed-Signal Integrated Circuit Testing: An Application of Current Testing Using the Upper Limit and the Lower Limit.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

1993
Design of testing circuit and test generation for built-in current testing.
Systems and Computers in Japan, 1993

Removal of redundancy in combinational circuits under classification of undetectable faults.
Systems and Computers in Japan, 1993

Test generation for multiple faults based on parallel vector pair analysis.
Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993

1992
A Testable Design of Logic Circuits under Highly Observable Condition.
IEEE Trans. Computers, 1992

Testable Designs of Sequential Circuits Under Highly Observable Condition.
Proceedings of the Proceedings IEEE International Test Conference 1992, 1992

Circuit Design for Built-in Current Testing.
Proceedings of the Proceedings IEEE International Test Conference 1992, 1992

Removal of Redundancy in Logic Circuits under Classification of Undetectable Faults.
Proceedings of the Digest of Papers: FTCS-22, 1992

1991
Stuck-open faults test generation for cmos combinational circuits.
Systems and Computers in Japan, 1991

An approach to the analysis and test of crosstalk faults in digital VLSI circuits.
Proceedings of the conference on European design automation, 1991

1990
Extended selection of switching target faults in CONT algorithm for test generation.
J. Electron. Test., 1990

On the evaluation of process-fault tolerance ability of CMOS integrated circuits.
Proceedings of the Proceedings IEEE International Test Conference 1990, 1990

Fault detection and diagnosis of k-UCP circuits under totally observable condition.
Proceedings of the 20th International Symposium on Fault-Tolerant Computing, 1990

1989
CONT: a concurrent test generation system.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1989

Test pattern generation for circuits with tri-state modules by Z-algorithm.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1989

Design of a BIST RAM with Row/Column Pattern Sensitive Fault Detection Capability.
Proceedings of the Proceedings International Test Conference 1989, 1989

Row/column pattern sensitive fault detection in RAMs via built-in self-test.
Proceedings of the Nineteenth International Symposium on Fault-Tolerant Computing, 1989

1986
Built-In Testing of Memory Using an On-Chip Compact Testing Scheme.
IEEE Trans. Computers, 1986

Test Pattern Generation for Circuits with Three-state Modules by Improved Z-algorithm.
Proceedings of the Proceedings International Test Conference 1986, 1986

1985
Test Pattern Generation for API Faults in RAM.
IEEE Trans. Computers, 1985

Design of Programmable Logic Arrays for Parallel Testing.
Comput. Syst. Sci. Eng., 1985

A Testable Design of Programmable Logic Arrays with Universal Control and Minimal Overhead.
Proceedings of the Proceedings International Test Conference 1985, 1985

1984
Built-in Testing of Memory Using On-chip Compact Testing Scheme.
Proceedings of the Proceedings International Test Conference 1984, 1984

1983
An Easily Testable Design of Programmable Logic Arrays for Multiple Faults.
IEEE Trans. Computers, 1983

Design of High-Level Test Language for Digital LSI.
Proceedings of the Proceedings International Test Conference 1983, 1983

Test generation for scan design circuits with tri-state modules and bidirectional terminals.
Proceedings of the 20th Design Automation Conference, 1983

1981
A Design of Programmable Logic Arrays with Universal Tests.
IEEE Trans. Computers, 1981

An integrated computer aided design system for gate array masterslices: Part 1. Logic reorganization system LORES-2.
Proceedings of the 18th Design Automation Conference, 1981

1979
On the Number of Fanout-Free Functions and Unate Cascade Functions.
IEEE Trans. Computers, 1979

Conservative Logic Elements and Their Universality.
IEEE Trans. Computers, 1979

1978
Cascade Realization of 3-Input 3-Output Conservative Logic Circuits.
IEEE Trans. Computers, 1978

Realization of Minimum Circuits with Two-Input Conservative Logic Elements.
IEEE Trans. Computers, 1978

Some Existence Theorems for Probabilistically Diagnosable Systems.
IEEE Trans. Computers, 1978

Connection Assignments for Probabilistically Diagnosable Systems.
IEEE Trans. Computers, 1978

On the Computational Complexity of System Diagnosis.
IEEE Trans. Computers, 1978

LORES - Logic Reorganization System.
Proceedings of the 15th Design Automation Conference, 1978

1976
On Magnetic Bubble Logic Circuits.
IEEE Trans. Computers, 1976

1975
Easily Testable Sequential Machines with Extra Inputs.
IEEE Trans. Computers, 1975

1974
Design of Diagnosable Sequential Machines Utilizing Extra Outputs.
IEEE Trans. Computers, 1974

1970
Sequential Machines Capable of Fault Diagnosis.
IEEE Trans. Computers, 1970


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