Shivendra Yadav

According to our database, Shivendra Yadav authored at least 5 papers between 2017 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2024

Passive Voltage Amplification in FE-FE-DE Heterostructure.

Bhaskar Awadhiya, Sameer Yadav, Yashwanth N., Abhishek Pahuja, Shivendra Yadav, Sachin Agrawal

IEEE Access, 2024

2022

Quantum Tunnelling and Themonic Emission, Transistor Simulation.

Shivendra Yadav, Deepak Joshi, Sanjib Kalita, Tushita Singh

Proceedings of the VLSI Design and Test - 26th International Symposium, 2022

2019

Performance improvement of nano wire TFET by hetero-dielectric and hetero-material: At device and circuit level.

Jyoti Patel, Dheeraj Sharma, Shivendra Yadav, Alemienla Lemtur, Priyanka Suman

Microelectron. J., 2019

GaAs-SiGe Based Novel Device Structure of Doping Less Tunnel FET.

Shivendra Yadav, Chithraja Rajan, Dheeraj Sharma, Sanjay Balotiya

Proceedings of the VLSI Design and Test - 23rd International Symposium, 2019

2017

Gate Metal Work Function Engineering for the Improvement of Electrostatic Behaviour of Doped Tunnel Field Effect Transistor.

Deepak Soni, Dheeraj Sharma, Shivendra Yadav, Mohd. Aslam, Dharmendra Singh Yadav, Neeraj Sharma

Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2017