Dheeraj Sharma

Orcid: 0000-0002-4046-5035

According to our database1, Dheeraj Sharma authored at least 18 papers between 2012 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2024
Reconfiguration of food grain supply network amidst COVID-19 outbreak: an emerging economy perspective.
Ann. Oper. Res., April, 2024

2022
Differential effects of online signals on sales performance of local brand clothing products.
J. Enterp. Inf. Manag., 2022

2021
Big data analytics and machine learning: A retrospective overview and bibliometric analysis.
Expert Syst. Appl., 2021

2019
Performance improvement of nano wire TFET by hetero-dielectric and hetero-material: At device and circuit level.
Microelectron. J., 2019

A Multi-Criteria Decision Making Approach for ranking Business Schools.
Int. J. Strateg. Decis. Sci., 2019

Approach on electrically doped TFET for suppression of ambipolar and improving RF performance.
IET Circuits Devices Syst., 2019

GaAs-SiGe Based Novel Device Structure of Doping Less Tunnel FET.
Proceedings of the VLSI Design and Test - 23rd International Symposium, 2019

Empirical Study on Malicious URL Detection Using Machine Learning.
Proceedings of the Distributed Computing and Internet Technology, 2019

2018
Online learning: Adoption, continuance, and learning outcome - A review of literature.
Int. J. Inf. Manag., 2018

Integrated fleet mix and routing decision for hazmat transportation: A developing country perspective.
Eur. J. Oper. Res., 2018

2017
Rhythm-based features for classification of focal and non-focal EEG signals.
IET Signal Process., 2017

A Comparative Study of GaP/SiGe Hetero Junction Double Gate Tunnel Field Effect Transistor.
Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2017

Gate Metal Work Function Engineering for the Improvement of Electrostatic Behaviour of Doped Tunnel Field Effect Transistor.
Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2017

2016
Design and Analysis of Novel InSb/Si Heterojunction Double Gate Tunnel Field Effect Transistor.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

A 0.9V, 3.1-10.6 GHz CMOS LNA with high gain and wideband input match in 90 nm CMOS process.
Proceedings of the 2016 IEEE Asia Pacific Conference on Circuits and Systems, 2016

2015
Analyses of DC and analog/RF performances for short channel quadruple-gate gate-all-around MOSFET.
Microelectron. J., 2015

Low power, high speed error tolerant multiplier using approximate adders.
Proceedings of the 19th International Symposium on VLSI Design and Test, 2015

2012
Analytical modeling for 3D potential distribution of rectangular gate (RecG) gate-all-around (GAA) MOSFET in subthreshold and strong inversion regions.
Microelectron. J., 2012


  Loading...