Shu-Shin Chin

According to our database, Shu-Shin Chin authored at least 8 papers between 2002 and 2006.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2006

Design and Implementation of Flexible Resampling Mechanism for High-Speed Parallel Particle Filters.

Sangjin Hong, Shu-Shin Chin, Petar M. Djuric, Miodrag Bolic

J. VLSI Signal Process., 2006

2005

Domain Specific Reconfigurable Processing Core Architecture for Digital Filtering Applications.

Sangjin Hong, Shu-Shin Chin

J. VLSI Signal Process., 2005

Extensible supply voltage control mechanism for low power array structure design.

Sangjin Hong, Shu-Shin Chin

IEEE Trans. Circuits Syst. II Express Briefs, 2005

2004

Power Reduction Technique in Coefficient Multiplications Through Multiplier Characterization.

Sangjin Hong, Shu-Shin Chin, Suhwan Kim, Wei Hwang

J. VLSI Signal Process., 2004

Incorporating Power Reduction Mechanism in Arithmetic Core Design.

Sangjin Hong, Shu-Shin Chin

Proceedings of the 2004 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2004), 2004

Usage of Application-Specific Switching Activity for Energy Minimization of Arithmetic Units.

Shu-Shin Chin, Sangjin Hong, Suhwan Kim

Proceedings of the 2004 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2004), 2004

Glitching power reduction through supply voltage adaptation mechanism for low power array structure design.

Sangjin Hong, Shu-Shin Chin, Magesh Sadasivam

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

2002

Multiplier architecture power consumption characterization for low-power DSP applications.

Sangjin Hong, Shu-Shin Chin, Suhwan Kim, Wei Hwang

Proceedings of the 2002 9th IEEE International Conference on Electronics, 2002