Suhwan Kim

According to our database1, Suhwan Kim authored at least 129 papers between 1998 and 2021.

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Bibliography

2021
A Controller PHY for Managed DRAM Solution With Damping-Resistor-Aided Pulse-Based Feed-Forward Equalizer.
IEEE J. Solid State Circuits, 2021

A 0.64-pJ/Bit 28-Gb/s/Pin High-Linearity Single-Ended PAM-4 Transmitter With an Impedance-Matched Driver and Three-Point ZQ Calibration for Memory Interface.
IEEE J. Solid State Circuits, 2021

A Differentiating Receiver With a Transition-Detecting DFE for Dual-Rank Mobile Memory Interface.
IEEE Access, 2021

A 1S Direct-Battery-Attach Integrated Buck Voltage Regulator with 5-Stack Thin-Gate 22nm FinFET CMOS Featuring Active Voltage Balancing and Cascaded Self-Turn-ON Drivers.
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021

Peak-Current-Controlled Ganged Integrated High-Frequency Buck Voltage Regulators in 22nm CMOS for Robust Cross-Tile Current Sharing.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021

Energy-Efficient Read-Out IC for High-Precision DC Measurement System with Instrumentation Amplifier Power Reduction Technique.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

A High-Accuracy and Fast-Correction Quadrature Signal Corrector Using an Adaptive Delay Gain Controller for Memory Interfaces.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

A Power-Efficient and Fast-Locking Digital Quadrature Clock Generator with Ping-Pong Phase Detection.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

GPU-Ether: GPU-native Packet I/O for GPU Applications on Commodity Ethernet.
Proceedings of the 40th IEEE Conference on Computer Communications, 2021

2020
A Digital Capacitive MEMS Microphone for Speech Recognition With Fast Wake-Up Feature Using a Sound Activity Detector.
IEEE Trans. Circuits Syst. II Express Briefs, 2020

A 0.45 pJ/b, 6.4 Gb/s Forwarded-Clock Receiver With DLL-Based Self-Tracking Loop for Unmatched Memory Interfaces.
IEEE Trans. Circuits Syst. II Express Briefs, 2020

A 0.83-pJ/Bit 6.4-Gb/s HBM Base Die Receiver Using a 45° Strobe Phase for Energy-Efficient Skew Compensation.
IEEE Trans. Circuits Syst. II Express Briefs, 2020

A Wide Dynamic Range Multi-Mode Band-Pass Continuous-Time Delta-Sigma Modulator Employing Single-Opamp Resonator With Positive Resistor-Feedback.
IEEE Trans. Circuits Syst. II Express Briefs, 2020

A 9Gb/s Wide Output Range Transmitter With 2D Binary-Segmented Driver and Dual-Loop Calibration for Intra-Panel Interfaces.
IEEE Trans. Circuits Syst. II Express Briefs, 2020

A 10.4-Gb/s 1-Tap Decision Feedback Equalizer With Different Pull-Up and Pull-Down Tap Weights for Asymmetric Memory Interfaces.
IEEE Trans. Circuits Syst. II Express Briefs, 2020

Data-Dependent Selection of Amplitude and Phase Equalization in a Quarter-Rate Transmitter for Memory Interfaces.
IEEE Trans. Circuits Syst. I Regul. Pap., 2020

A 0.3 lx-1.4 Mlx Monolithic Silicon Nanowire Light-to-Digital Converter With Temperature-Independent Offset Cancellation.
IEEE J. Solid State Circuits, 2020

A 28-Gb/s/pin PAM-4 Single-Ended Transmitter with High-Linearity and Impedance-Matched Driver and 3-Point ZQ Calibration for Memory Interfaces.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020

A Sub-1 ppm/°C CMOS Bandgap Voltage Reference With Process Tolerant Piecewise Second-Order Curvature Compensation.
Proceedings of the 33rd IEEE International System-on-Chip Conference, 2020

Self-Powered IOT System for Edge Inference.
Proceedings of the 21st International Symposium on Quality Electronic Design, 2020

Digital Control of Switching and Linear Integrated Voltage Regulators.
Proceedings of the 2020 IEEE Custom Integrated Circuits Conference, 2020

A 0.4-1.7GHz Wide Range Fractional-N PLL Using a Transition-Detection DAC for Jitter Reduction.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2020

2019
A Quadrature Clock Corrector for DRAM Interfaces, With a Duty-Cycle and Quadrature Phase Detector Based on a Relaxation Oscillator.
IEEE Trans. Very Large Scale Integr. Syst., 2019

An 80.2 dB DR 23.25 mW/Channel 8-Channel Ultrasound Receiver With a Beamforming Embedded SAR ADC.
IEEE Trans. Circuits Syst. II Express Briefs, 2019

A 12.8-Gb/s Quarter-Rate Transmitter Using a 4: 1 Overlapped Multiplexing Driver Combined With an Adaptive Clock Phase Aligner.
IEEE Trans. Circuits Syst. II Express Briefs, 2019

A Light-Load Efficient Fully Integrated Voltage Regulator in 14-nm CMOS With 2.5-nH Package-Embedded Air-Core Inductors.
IEEE J. Solid State Circuits, 2019

A 22-bit Read-Out IC With 7-ppm INL and Sub-100-µHz 1/ f Corner for DC Measurement Systems.
IEEE J. Solid State Circuits, 2019

A 370-fJ/b, 0.0056 mm<sup>2</sup>/DQ, 4.8-Gb/s DQ Receiver for HBM3 with a Baud-Rate Self-Tracking Loop.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

A Sound Activity Detector Embedded Low-Power MEMS Microphone Readout Interface for Speech Recognition.
Proceedings of the 2019 IEEE/ACM International Symposium on Low Power Electronics and Design, 2019

A Low-Power and Low-Noise 20: 1 Serializer with Two Calibration Loops in 55-nm CMOS.
Proceedings of the 2019 IEEE/ACM International Symposium on Low Power Electronics and Design, 2019

A 16 Bit Incremental ADC with Swapping DAC for Low Power Sensor Applications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

A 20Gb/s Dual-Mode PAM4/NRZ Single-Ended Transmitter with RLM Compensation.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

2018
An Uncooled Microbolometer Infrared Imager With a Shutter-Based Successive-Approximation Calibration Loop.
IEEE Trans. Very Large Scale Integr. Syst., 2018

A 2-MHz BW 82-dB DR Continuous-Time Delta-Sigma Modulator With a Capacitor-Based Voltage DAC for ELD Compensation.
IEEE Trans. Very Large Scale Integr. Syst., 2018

A 4266 Mb/s/pin LPDDR4 Interface With An Asynchronous Feedback CTLE and An Adaptive 3-Step Eye Detection Algorithm for Memory Controller.
IEEE Trans. Circuits Syst. II Express Briefs, 2018

A 1.2-V 108.9-dB A-Weighted DR 101.4-dB SNDR Audio ΣΔ ADC Using a Multi-Rate Noise-Shaping Quantizer.
IEEE Trans. Circuits Syst. II Express Briefs, 2018

A 2.1-Gb/s 12-Channel Transmitter With Phase Emphasis Embedded Serializer for 55-in UHD Intra-Panel Interface.
IEEE J. Solid State Circuits, 2018

A 3.2 Gb/s 16-Channel Transmitter for Intra-Panel Interfaces, With Independently Controllable Output Swing, Common-Mode Voltage, and Equalization.
IEEE Access, 2018

A Single-Stage, Single-Inductor, 6-Input 9-Output Multi-Modal Energy Harvesting Power Management IC for 100µW-120MW Battery-Powered IoT Edge Nodes.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018


A 21.8b sub-100μHz 1/f corner 2.4μV-offset programmable-gain read-out IC for bridge measurement systems.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

Energy-Efficient Dynamic Comparator with Active Inductor for Receiver of Memory Interfaces.
Proceedings of the International Symposium on Low Power Electronics and Design, 2018

A 99.2% Tracking Accuracy Single-Inductor Quadruple-Input-Quadruple-Output Buck-Boost Converter Topology with Periodical Interval Perturbation and Observation MPPT.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018

2017
A low-pass continuous-time delta-sigma interface circuit for wideband MEMS gyroscope readout ASIC.
Proceedings of the 30th IEEE International System-on-Chip Conference, 2017

A constant bandwidth switched-capacitor programmable-gain amplifier utilizing adaptive miller compensation technique.
Proceedings of the 30th IEEE International System-on-Chip Conference, 2017

An 8Gb/s adaptive DFE with level calibration using training data pattern for mobile DRAM interface.
Proceedings of the International SoC Design Conference, 2017

A 0.13pJ/bit, referenceless transceiver with clock edge modulation for a wired intra-BAN communication.
Proceedings of the 2017 IEEE/ACM International Symposium on Low Power Electronics and Design, 2017

Power efficient SAR ADC adaptive to input activity for ECG monitoring applications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

A load variation tolerant readout interface for high linear MEMS capacitive microphones.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

A 2.1Gbps 12-channel transmitter with phase emphasis embedded serializer for UHD intra-panel interface.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017

A 12.1mW, 60dB SNR, 8-channel beamforming embedded SAR ADC for ultrasound imaging systems.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017

2016
A Sub-1.0-V On-Chip CMOS Thermometer With a Folded Temperature Sensor for Low-Power Mobile DRAM.
IEEE Trans. Circuits Syst. II Express Briefs, 2016

Column readout circuit with dual integration CDS for infrared imagers.
IEICE Electron. Express, 2016

A CMOS analog front-end for driving a high-speed SAR ADC in low-power ultrasound imaging systems.
Proceedings of the 29th IEEE International System-on-Chip Conference, 2016

A current-mirror technique used for high-order curvature compensated bandgap reference in automotive application.
Proceedings of the IEEE 59th International Midwest Symposium on Circuits and Systems, 2016

A 386-μW, 15.2-bit Programmable-Gain Embedded Delta-Sigma ADC for Sensor Applications.
Proceedings of the 2016 International Symposium on Low Power Electronics and Design, 2016

Phase shift keying demodulator with decision feedback phase-locked loop.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

2015
Differentiating ASK Demodulator for Contactless Smart Cards Supporting VHBR.
IEEE Trans. Circuits Syst. II Express Briefs, 2015

Dual-source hysteretic switched-inductor 0.18 µm complementary metal-oxide-semiconductor charger-supply system.
IET Circuits Devices Syst., 2015

Low noise output stage for oversampling audio DAC.
Proceedings of the 28th IEEE International System-on-Chip Conference, 2015

A 9-bit, 110-MS/s pipelined-SAR ADC using time-interleaved technique with shared comparator.
Proceedings of the 28th IEEE International System-on-Chip Conference, 2015

A 1.74mW/GHz 0.11-2.5GHz fast-locking, jitter-reducing, 180° phase-shift digital DLL with a window phase detector for LPDDR4 memory controllers.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2015

2014
1.2 V 10-bit 75 MS/s Pipelined ADC With Phase-Dependent Gain-Transition CDS.
IEEE Trans. Very Large Scale Integr. Syst., 2014

On the Optimal Deployment of Direction Finders.
IEEE Trans Autom. Sci. Eng., 2014

23.4 Dual-source single-inductor 0.18μm CMOS charger-supply with nested hysteretic and adaptive on-time PWM control.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

Autonomous dynamic driving control of wheeled mobile robots.
Proceedings of the 2014 IEEE International Conference on Robotics and Automation, 2014

2013
Bitline Techniques With Dual Dynamic Nodes for Low-Power Register Files.
IEEE Trans. Circuits Syst. I Regul. Pap., 2013

A 10-Mbps 0.8-pJ/bit Referenceless Clock and Data Recovery Circuit for Optically Controlled Neural Interface System.
IEEE Trans. Circuits Syst. II Express Briefs, 2013

Performance of a Distributed Simultaneous Strain and Temperature Sensor Based on a Fabry-Perot Laser Diode and a Dual-Stage FBG Optical Demultiplexer.
Sensors, 2013

A Process-Variation-Tolerant On-Chip CMOS Thermometer for Auto Temperature Compensated Self-Refresh of Low-Power Mobile DRAM.
IEEE J. Solid State Circuits, 2013

High-resolution and wide-dynamic range time-to-digital converter with a multi-phase cyclic Vernier delay line.
Proceedings of the ESSCIRC 2013, 2013

A 32-channel neural recording system with a liquid-crystal polymer MEA.
Proceedings of the 2013 IEEE Biomedical Circuits and Systems Conference (BioCAS), Rotterdam, The Netherlands, October 31, 2013

2012
Power-Gating Noise Minimization by Three-Step Wake-Up Partitioning.
IEEE Trans. Circuits Syst. I Regul. Pap., 2012

Integrating Metal-Oxide-Decorated CNT Networks with a CMOS Readout in a Gas Sensor.
Sensors, 2012

Simultaneous Measurement of Neural Spike Recordings and Multi-Photon Calcium Imaging in Neuroblastoma Cells.
Sensors, 2012

Non-Destructive Inspection Methods for LEDs Using Real-Time Displaying Optical Coherence Tomography.
Sensors, 2012

Static-switching pulse domino: A switching-aware design technique for wide fan-in dynamic multiplexers.
Integr., 2012

Neural recording system with low-noise analog front-end and comparator-based cyclic ADC.
Proceedings of the IEEE 25th International SOC Conference, 2012

Efficiency of switched-inductor dc-dc converter ICs across process technologies.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

2011
Improving the Accuracy of Capacitance-to-Frequency Converter by Accumulating Residual Charges.
IEEE Trans. Instrum. Meas., 2011

A Delta-Sigma Interface Circuit for Capacitive Sensors With an Automatically Calibrated Zero Point.
IEEE Trans. Circuits Syst. II Express Briefs, 2011

A Low-Cost and Low-Power Time-to-Digital Converter Using Triple-Slope Time Stretching.
IEEE Trans. Circuits Syst. II Express Briefs, 2011

A 1.0-4.0-Gb/s All-Digital CDR With 1.0-ps Period Resolution DCO and Adaptive Proportional Gain Control.
IEEE J. Solid State Circuits, 2011

A 4.8Gb/s impedance-matched bidirectional multi-drop transceiver for high-capacity memory interface.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011

Extracting the frequency response of switching DC-DC converters in CCM and DCM from time-domain simulations.
Proceedings of the International SoC Design Conference, 2011

A comparator-based cyclic analog-to-digital converter with boosted preset voltage.
Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011

A CMOs readout integrated circuit with wide dynamic range for a CNT bio-sensor array system.
Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011

A low-power referenceless clock and data recovery circuit with clock-edge modulation for biomedical sensor applications.
Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011

Harvesting circuits for miniaturized photovoltaic cells.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

Multi-channel noise reduction with beamforming and masking-based Wiener filtering for human-robot interface.
Proceedings of the 5th International Conference on Automation, Robotics and Applications, 2011

A static-switching pulse domino technique for statistical power reduction of wide fan-in dynamic gates.
Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011

2010
A fast-acquisition PLL using split half-duty sampled feedforward loop filter.
IEEE Trans. Consumer Electron., 2010

A 14.6 ps Resolution, 50 ns Input-Range Cyclic Time-to-Digital Converter Using Fractional Difference Conversion Method.
IEEE Trans. Circuits Syst. I Regul. Pap., 2010

Charge Amplifier With an Enhanced Frequency Response for SPM-Based Data Storage.
IEEE Trans. Circuits Syst. II Express Briefs, 2010

A 0.3-1.4 GHz All-Digital Fractional-N PLL With Adaptive Loop Gain Controller.
IEEE J. Solid State Circuits, 2010

A high-resolution and fast-conversion readout circuit for differential capacitive sensors.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010

Footer voltage feedforward domino technique for wide fan-in dynamic logic.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010

A three-step power-gating turn-on technique for controlling ground bounce noise.
Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010

2009
High-speed 10-bit LCD column driver with a split DAC and a class-AB output buffer.
IEEE Trans. Consumer Electron., 2009

A High-Speed Range-Matching TCAM for Storage-Efficient Packet Classification.
IEEE Trans. Circuits Syst. I Regul. Pap., 2009

Achieving High Efficiency Under Micro-Watt Loads with Switching Buck DC-DC Converters.
J. Low Power Electron., 2009

A PVT-insensitive time-to-digital converter using fractional difference Vernier delay lines.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2009, 2009

A high resolution capacitance deviation-to-digital converter utilizing time stretching.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2009, 2009

Single-inductor dual-input dual-output buck-boost fuel-cell-li-ion charging DC-DC converter supply.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009

2007
A Multi-Mode Power Gating Structure for Low-Voltage Deep-Submicron CMOS ICs.
IEEE Trans. Circuits Syst. II Express Briefs, 2007

Introduction to the Special Issue on the 2006 Asian Solid-State Circuits Conference (A-SSCC'06).
IEEE J. Solid State Circuits, 2007

A 0.25-µm CMOS 1.9-GHz PHS RF Transceiver With a 150-kHz Low-IF Architecture.
IEEE J. Solid State Circuits, 2007

A 2.8Gb/s All-Digital CDR with a 10b Monotonic DCO.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

2006
A Storage- and Power-Efficient Range-Matching TCAM for Packet Classification.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

2005
Charge-Recovery Computing on Silicon.
IEEE Trans. Computers, 2005

Fast, efficient, recovering, and irreversible.
Proceedings of the Second Conference on Computing Frontiers, 2005

2004
Power Reduction Technique in Coefficient Multiplications Through Multiplier Characterization.
J. VLSI Signal Process., 2004

A synchronous interface for SoCs with multiple clock domains.
Proceedings of the Proceedings 2004 IEEE International SOC Conference, 2004

Usage of Application-Specific Switching Activity for Energy Minimization of Arithmetic Units.
Proceedings of the 2004 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2004), 2004

Experimental measurement of a novel power gating structure with intermediate power saving mode.
Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004

2003
A true single-phase energy-recovery multiplier.
IEEE Trans. Very Large Scale Integr. Syst., 2003

Application of an SOI 0.12-µm CMOS technology to SoCs with low-power and high-frequency circuits.
IBM J. Res. Dev., 2003

Low-power circuits and technology for wireless digital systems.
IBM J. Res. Dev., 2003

Fine-grain real-time reconfigurable pipelining.
IBM J. Res. Dev., 2003

A clockless future for systems on chip.
IEEE Des. Test Comput., 2003

Understanding and minimizing ground bounce during mode transition of power gating structures.
Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003

2002
Low-power Application-specific Parallel Array Multiplier Design for DSP Applications.
VLSI Design, 2002

Multiplier architecture power consumption characterization for low-power DSP applications.
Proceedings of the 2002 9th IEEE International Conference on Electronics, 2002

2001
True single-phase adiabatic circuitry.
IEEE Trans. Very Large Scale Integr. Syst., 2001

A resonant clock generator for single-phase adiabatic systems.
Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001

A True Single-Phase 8-bit Adiabatic Multiplier.
Proceedings of the 38th Design Automation Conference, 2001

Design, Verification, and Test of a True Single-Phase 8-bit Adiabatic Multiplier.
Proceedings of the 19th Conference on Advanced Research in VLSI (ARVLSI 2001), 2001

1999
Single-phase source-coupled adiabatic logic.
Proceedings of the 1999 International Symposium on Low Power Electronics and Design, 1999

1998
True single-phase energy-recovering logic for low-power, high-speed VLSI.
Proceedings of the 1998 International Symposium on Low Power Electronics and Design, 1998


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