Shumpei Morita

According to our database, Shumpei Morita authored at least 9 papers between 2016 and 2022.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2022

Efficient Analysis for Mitigation of Workload-Dependent Aging Degradation.

Shumpei Morita, Song Bian, Michihiro Shintani, Takashi Sato

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

2018

A study on NBTI-induced delay degradation considering stress frequency dependence.

Zuitoku Shin, Shumpei Morita, Song Bian, Michihiro Shintani, Masayuki Hiromoto, Takashi Sato

Proceedings of the 19th International Symposium on Quality Electronic Design, 2018

Efficient worst-case timing analysis of critical-path delay under workload-dependent aging degradation.

Shumpei Morita, Song Bian, Michihiro Shintani, Masayuki Hiromoto, Takashi Sato

Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

2017

Scalable Device Array for Statistical Characterization of BTI-Related Parameters.

Hiromitsu Awano, Shumpei Morita, Takashi Sato

IEEE Trans. Very Large Scale Integr. Syst., 2017

Utilization of Path-Clustering in Efficient Stress-Control Gate Replacement for NBTI Mitigation.

Shumpei Morita, Song Bian, Michihiro Shintani, Masayuki Hiromoto, Takashi Sato

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017

Identification and Application of Invariant Critical Paths under NBTI Degradation.

Song Bian, Shumpei Morita, Michihiro Shintani, Hiromitsu Awano, Masayuki Hiromoto, Takashi Sato

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017

Comparative study of path selection and objective function in replacing NBTI mitigation logic.

Shumpei Morita, Song Bian, Michihiro Shintani, Masayuki Hiromoto, Takashi Sato

Proceedings of the 18th International Symposium on Quality Electronic Design, 2017

2016

Nonlinear delay-table approach for full-chip NBTI degradation prediction.

Song Bian, Michihiro Shintani, Shumpei Morita, Masayuki Hiromoto, Takashi Sato

Proceedings of the 17th International Symposium on Quality Electronic Design, 2016

Workload-Aware Worst Path Analysis of Processor-Scale NBTI Degradation.

Song Bian, Michihiro Shintani, Shumpei Morita, Hiromitsu Awano, Masayuki Hiromoto, Takashi Sato

Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016